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参数资料
| 型号： | DC570A |
| 厂商： | Linear Technology |
| 文件页数： | 3/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2440 |
| 软件下载： | QuikEval System |
| 设计资源： | DC570A Design File DC570A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 3.5k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2440 |
| 已供物品： | 板 |
| 相关产品： | LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP |
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LTC2440
11
2440fd
APPLICATIONS INFORMATION
Figure 3. Output Data Timing
0.5 VREF where VREF = REF+ – REF–. Outside this range,
the converter indicates the overrange or the underrange
condition using distinct output codes.
Output Data Format
The LTC2440 serial output data stream is 32-bits long.
The rst 3-bits represent status information indicating
the sign and conversion state. The next 24-bits are the
conversion result, MSB rst. The remaining 5-bits are
sub LSBs beyond the 24-bit level that may be included in
averaging or discarded without loss of resolution. In the
case of ultrahigh resolution modes, more than 24 effec-
tive bits of performance are possible (see Table 3). Under
these conditions, sub LSBs are included in the conversion
result and represent useful information beyond the 24-bit
level. The third and fourth bit together are also used to
indicate an underrange condition (the differential input
voltage is below –FS) or an overrange condition (the dif-
ferential input voltage is above +FS). For input conditions
in excess of twice full scale (|VIN| ≥ VREF), the converter
may indicate either overrange or underrange. Once the
input returns to the normal operating range, the conversion
result is immediately accurate within the specications of
the device.
Bit 31 (rst output bit) is the end of conversion (EOC)
indicator. This bit is available at the SDO pin during the
conversion and sleep states whenever the CS pin is LOW.
This bit is HIGH during the conversion and goes LOW
when the conversion is complete.
Bit 30 (second output bit) is a dummy bit (DMY) and is
always LOW.
Bit 29 (third output bit) is the conversion result sign
indicator (SIG). If VIN is >0, this bit is HIGH. If VIN is <0,
this bit is LOW.
Bit 28 (fourth output bit) is the most signicant bit (MSB) of
the result. This bit in conjunction with Bit 29 also provides
the underrange or overrange indication. If both Bit 29 and
Bit 28 are HIGH, the differential input voltage is above +FS.
If both Bit 29 and Bit 28 are LOW, the differential input
voltage is below –FS.
The function of these bits is summarized in Table 1.
Table 1. LTC2440 Status Bits
Input Range
Bit 31
EOC
Bit 30
DMY
Bit 29
SIG
Bit 28
MSB
VIN ≥ 0.5 VREF
0011
0V ≤ VIN < 0.5 VREF
0010
–0.5 VREF ≤ VIN < 0V
0001
VIN < –0.5 VREF
0000
Bits ranging from 28 to 5 are the 24-bit conversion result
MSB rst.
Bit 5 is the Least Signicant Bit (LSB).
Bits ranging from 4 to 0 are sub LSBs below the 24-bit
level. Bits 4 to bit 0 may be included in averaging or dis-
carded without loss of resolution.
Data is shifted out of the SDO pin under control of the
serial clock (SCK), see Figure 3. Whenever CS is HIGH,
SDO remains high impedance.
In order to shift the conversion result out of the device,
CS must rst be driven LOW. EOC is seen at the SDO pin
of the device once CS is pulled LOW. EOC changes real
time from HIGH to LOW at the completion of a conversion.
This signal may be used as an interrupt for an external
MSB
SIG
“0”
1
2
3
4
5
262732
BIT 0
BIT 27
BIT 5
LSB24
BIT 28
BIT 29
BIT 30
SDO
SCK
BUSY
CS
EOC
BIT 31
SLEEP
DATA OUTPUT
CONVERSION
2440 F03
Hi-Z
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