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参数资料
| 型号： | DC570A |
| 厂商： | Linear Technology |
| 文件页数： | 27/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2440 |
| 软件下载： | QuikEval System |
| 设计资源： | DC570A Design File DC570A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 2 |
| 位数： | 24 |
| 采样率（每秒）： | 3.5k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2440 |
| 已供物品： | 板 |
| 相关产品： | LTC2440CGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TRPBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN#PBF-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440IGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440CGN#TR-ND - IC CONV A/D 24-BIT DIFF 16-SSOP LTC2440IGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP LTC2440CGN-ND - IC ADC DIFFER 24-BIT HS 16-SSOP |
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LTC2440
8
2440fd
PIN FUNCTIONS
GND (Pins 1, 8, 9, 16): Ground. Multiple ground pins
internally connected for optimum ground current ow and
VCCdecoupling.Connecteachoneofthesepinstoaground
plane through a low impedance connection. All four pins
must be connected to ground for proper operation.
VCC (Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1) with a 10μF tantalum capacitor in parallel with 0.1μF
ceramic capacitor as close to the part as possible.
REF+ (Pin 3), REF– (Pin 4):
Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
is maintained more positive than the reference negative
input, REF–, by at least 0.1V.
IN+ (Pin 5), IN– (Pin 6): Differential Analog Input. The
voltage on these pins can have any value between GND
– 0.3V and VCC + 0.3V. Within these limits the converter
bipolar input range (VIN = IN+ – IN–) extends from –0.5
(VREF) to 0.5 (VREF). Outside this input range the
converter produces unique overrange and underrange
output codes.
SDI (Pin 7): Serial Data Input. This pin is used to select
the speed/resolution of the converter. If SDI is grounded
(pin compatible with LTC2410) the device outputs data at
880Hz with 21 bits effective resolution. By tying SDI HIGH,
the converter enters the ultralow noise mode (200nVRMS)
with simultaneous 50/60Hz rejection at 6.9Hz output
rate. SDI may be driven logic HIGH or LOW anytime dur-
ing the conversion or sleep state in order to change the
speed/resolution. The conversion immediately following
the data output cycle will be valid and performed at the
newly selected output rate/resolution. SDI may also be
programmed by a serial input data stream under control of
SCK during the data output cycle. One of ten speed/resolu-
tion ranges (from 6.9Hz/200nVRMS to 3.5kHz/21μVRMS)
may be selected. The rst conversion following a new
selection is valid and performed at the newly selected
speed/resolution.
EXT (Pin 10): Internal/External SCK Selection Pin. This pin
is used to select internal or external SCK for outputting
data. If EXT is tied low (pin compatible with the LTC2410),
the device is in the external SCK mode and data is shifted
out the device under the control of a user applied serial
clock. If EXT is tied high, the internal serial clock mode
is selected. The device generates its own SCK signal and
outputs this on the SCK pin. A framing signal BUSY (Pin 15)
goes low indicating data is being output.
CS (Pin 11): Active LOW Digital Input. A LOW on this pin
enables the SDO digital output and wakes up the ADC.
Following each conversion the ADC automatically enters
the Sleep mode and remains in this low power state as
long as CS is HIGH. A LOW-to-HIGH transition on CS
during the Data Output transfer aborts the data transfer
and starts a new conversion.
SDO (Pin 12): Three-State Digital Output. During the Data
Output period, this pin is used as serial data output. When
the chip select CS is HIGH (CS = VCC) the SDO pin is in a
high impedance state. During the Conversion and Sleep
periods, this pin is used as the conversion status output. The
conversion status can be observed by pulling CS LOW.
SCK (Pin 13): Bidirectional Digital Clock Pin. In Internal
Serial Clock Operation mode, SCK is used as digital output
for the internal serial interface clock during the Data Output
period. In External Serial Clock Operation mode, SCK is used
as digital input for the external serial interface clock during
the Data Output period. The Serial Clock Operation mode is
determined by the logic level applied to the EXT pin.
fO (Pin 14): Frequency Control Pin. Digital input that con-
trols the internal conversion clock. When fO is connected to
VCC or GND, the converter uses its internal oscillator running
at 9MHz. The conversion rate is determined by the selected
OSR such that tCONV (in ms) = (40 OSR + 170)/9000
(tCONV = 1.137ms at OSR = 256, tCONV = 146ms at OSR =
32768). The rst null is located at 8/tCONV, 7kHz at OSR =
256 and 55Hz (simultaneous 50/60Hz) at OSR = 32768.
When fO is driven by an oscillator with frequency fEOSC (in
kHz), the conversion time becomes tCONV = (40 OSR +
170)/fEOSC (in ms) and the rst null remains 8/tCONV.
BUSY (Pin 15): Conversion in Progress Indicator. For
compatibility with the LTC2410, this pin should not be
tied to ground. This pin is HIGH while the conversion
is in progress and goes LOW indicating the conversion
is complete and data is ready. It remains low during the
sleep and data output states. At the conclusion of the data
output state, it goes HIGH indicating a new conversion
has begun.
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