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参数资料
| 型号： | DC823B-B |
| 厂商： | Linear Technology |
| 文件页数： | 9/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL LTM4600HV |
| 软件下载： | LTM4600HV Spice Model |
| 设计资源： | DC823B-B Design Files DC823B-B Schematic |
| 标准包装： | 1 |
| 系列： | µModule® |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 1，非隔离 |
| 输出电压： | 0.6V，1.2V，1.5V，1.8V，2.5V，3.3V，和 5V |
| 电流 - 输出： | 10A（最小值） |
| 输入电压： | 4.5 ~ 28 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 1.35MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | LTM4600HV |
| 相关产品： | LTM4600HVIV#PBF-ND - IC DC/DC UMODULE 10A 104-LGA LTM4600HVEV#PBF-ND - IC DC/DC UMODULE 10A 104-LGA |
LTM4600HV
APPLICATIO S I FOR ATIO
The typical LTM4600HV application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage.
voltage is margined up. The output voltage is margined
down when Q DOWN is on and Q UP is off. If the output
voltage V O needs to be margined up/down by ±M%, the
resistor values of R UP and R DOWN can be calculated from
Output Voltage Programming and Margining
The PWM controller of the LTM4600HV has an internal
0.6V±1% reference voltage. As shown in the block diagram,
the following equations:
(R SET R UP ) ? V O ?(1 + M%)
( R SET R UP ) + 100 k Ω
= 0 . 6 V
a 100k/0.5% internal feedback resistor connects V OUT
and V OSET pins. Adding a resistor R SET from V OSET pin to
SGND pin programs the output voltage:
R SET ? V O ?( 1 – M %)
R SET + ( 100 k Ω R DOWN )
= 0 . 6 V
V O = 0 . 6 V ?
100k + R SET
R SET
Input Capacitors
The LTM4600HV μModule should be connected to a low
Table 1 shows the standard values of 1% R SET resistor
for typical output voltages:
Table 1 .
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 21, the bulk input capacitor C IN is selected
R SET
(k Ω )
V O
(V)
Open
0.6
100
1.2
66.5
1.5
49.9
1.8
43.2
2
31.6
2.5
22.1
3.3
13.7
5
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
D =
V O
V IN
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
function with the LTM4600HV. In addition to the feedback
resistor R SET , several external components are added.
Turn off both transistor Q UP and Q DOWN to disable the
I CIN ( RMS ) =
I O (MAX)
η %
? D ?( 1 ? D )
margining. When Q UP is on and Q DOWN is off, the output
In the above equation, η % is the estimated ef?ciency of
the power module. C1 can be a switcher-rated electrolytic
LTM4600HV
V OUT
R DOWN
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
PGND
100k
SGND
V OSET
R SET
Q DOWN
2N7002
R UP
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements over temperature.
Q UP
2N7002
4600hv F02
Figure 2. LTM4600HV Margining Implementation
In Figure 21, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R (for extended temperature range), 10μF ceramic
capacitors are recommended. This decoupling capacitor
4600hvfc
9
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