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参数资料
| 型号： | DC847A |
| 厂商： | Linear Technology |
| 文件页数： | 3/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2446 |
| 软件下载： | QuikEval System |
| 设计资源： | DC847A Design File DC847A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2446 |
| 已供物品： | 板 |
| 相关产品： | LTC2446CUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446CUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN |
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LTC2446/LTC2447
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Serial Clock Input/Output (SCK)
The serial clock signal present on SCK (Pin 38) is used to
synchronize the data transfer. Each bit of data is shifted out
the SDO pin on the falling edge of the serial clock.
In the Internal SCK mode of operation, the SCK pin is an
output and the LTC2446/LTC2447 create their own serial
clock. In the External SCK mode of operation, the SCK pin
is used as input. The internal or external SCK mode is
selected by tying EXT (Pin 3) LOW for external SCK and
HIGH for internal SCK.
Serial Data Output (SDO)
The serial data output pin, SDO (Pin 37), provides the
result of the last conversion as a serial bit stream (MSB
first) during the data output state. In addition, the SDO pin
is used as an end of conversion indicator during the
conversion and sleep states.
When CS (Pin 36) is HIGH, the SDO driver is switched to
a high impedance state. This allows sharing the serial
interface with other devices. If CS is LOW during the
convert or sleep state, SDO will output EOC. If CS is LOW
during the conversion phase, the EOC bit appears HIGH on
the SDO pin. Once the conversion is complete, EOC goes
LOW. The device remains in the sleep state until the first
rising edge of SCK occurs while CS = LOW.
Chip Select Input (CS)
The active LOW chip select, CS (Pin 36), is used to test the
conversion status and to enable the data output transfer as
described in the previous sections.
In addition, the CS signal can be used to trigger a new
conversion cycle before the entire serial data transfer has
been completed. The LTC2446/LTC2447 will abort any
serial data transfer in progress and start a new conversion
cycle anytime a LOW-to-HIGH transition is detected at the
CS pin after the converter has entered the data output
state.
Serial Data Input (SDI)
The serial data input (SDI, Pin 34) is used to select the
speed/resolution input channel and reference of the
LTC2446/LTC2447. SDI is programmed by a serial input
data stream under the control of SCK during the data
output cycle, see Figure 3.
Initially, after powering up, the device performs a conver-
sion with IN+ = CH0, IN– = CH1, REF+ = VREF01+, REF– =
VREF01–, OSR = 256 (output rate nominally 880Hz), and 1x
speed mode (no Latency). Once this first conversion is
complete, the device enters the sleep state and is ready to
output the conversion result and receive the serial data input
stream programming the speed/resolution, input channel
and reference for the next conversion. At the conclusion of
each conversion cycle, the device enters this state.
In order to change the speed/resolution, reference or input
channel, the first 3 bits shifted into the device are 101. This
is compatible with the programming sequence of the
LTC2414/LTC2418/LTC2444/LTC2445/LTC2448/
LTC2449. If the sequence is set to 000 or 100, the follow-
ing input data is ignored (don’t care) and the previously
selected speed/resolution, channel and reference remain
valid for the next conversion. Combinations other than 101,
100, and 000 of the 3 control bits should be avoided.
If the first 3 bits shifted into the device are 101, then the
following 5 bits select the input channel/reference for the
following conversion (see Table 3). The next 5 bits select
the speed/resolution and mode 1x (no Latency) 2x (double
output rate with one conversion latency), see Table 4. If
these 5 bits are set to all 0’s, the previous speed remains
selected for the next conversion. This is useful in applica-
tions requiring a fixed output rate/resolution but need to
change the input channel or reference. In this case, the
timing and input sequence is compatible with the LTC2414/
LTC2418.
When an update operation is initiated (the first 3 bits are
101) the next 5 bits are the channel/reference address. The
first bit, SGL, determines if the input selection is differen-
tial (SGL = 0) or single-ended (SGL = 1). For SGL = 0, two
adjacent channels can be selected to form a differential
input. For SGL = 1, one of 8 channels is selected as the
positive input. The negative input is COM for all single
ended operations. The global VREF bit (GLBL) is used to
determine which reference is selected. GLBL = 0 selects
the individual reference slaved to a given channel. Each set
of channels has a corresponding differential input refer-
ence. If GLBL = 1, a global reference VREFG+/VREFG– is
selected. The global reference input may be used for any
input channel selected. Table 3 shows a summary of input/
reference selection. The remaining bits (ODD, A1, A0)
determine which channel is selected.
APPLICATIO S I FOR ATIO
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