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参数资料
| 型号： | DC847A |
| 厂商： | Linear Technology |
| 文件页数： | 8/28页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2446 |
| 软件下载： | QuikEval System |
| 设计资源： | DC847A Design File DC847A Schematic |
| 标准包装： | 1 |
| 系列： | QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 24 |
| 采样率（每秒）： | 8k |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 已用 IC / 零件： | LTC2446 |
| 已供物品： | 板 |
| 相关产品： | LTC2446CUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#PBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446IUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN LTC2446CUHF#TRPBF-ND - IC ADC 24BIT 8CH HI SPEED 38QFN |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
LTC2446/LTC2447
16
24467fa
output sequence is aborted prior to the 13th rising edge of
SCK, the new input data is ignored, and the previously
selected speed/resolution and channel are used for the
next conversion cycle. This is useful for systems not
requiring all 32 bits of output data, aborting an invalid
conversion cycle or synchronizing the start of a conver-
sion. If a new channel is being programmed, the rising
edge of CS must come after the 14th falling edge of SCK
in order to store the data input sequence.
CS
SCK
(EXTERNAL)
SDI
SDO
BUSY
12345
6
15
MSB
BIT 28 BIT 27 BIT 26 BIT 25
SIG
BIT 29
“0”
BIT 30
EOC
Hi-Z
BIT 31
24467 F05
CONVERSION
SLEEP
DATA OUTPUT
CONVERSION
TEST EOC
DON'T CARE
VCC
FO
REF67+
REF67–
CH0
CH1
CH2
CH7
COM
REFG+
REFG–
REF01+
REF01–
SCK
SDI
SDO
CS
GND
28
29
30
11
10
35
24
23
8
9
12
22
7
38
37
1,4,5,6,31,32,33
36
34
USER SELECTABLE
REFERENCES
0.1V TO VCC
ANALOG
INPUTS
...
2
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
1
F
4.5V TO 5.5V
LTC2446
4-WIRE
SPI INTERFACE
BUSY
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status on the SDO pin.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the fifth falling edge and the
32nd falling edge of SCK, see Figure 5. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. Thirteen serial input
data bits are required in order to properly program the
speed/resolution and input/reference channel. If the data
APPLICATIO S I FOR ATIO
WU
U
Figure 5. External Serial Clock, Reduced Output Data Length
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