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| 型号： | DC941A |
| 厂商： | Linear Technology |
| 文件页数： | 5/32页 |
| 文件大小： | 0K |
| 描述： | BOARD DELTA SIGMA ADC LTC2482 |
| 软件下载： | QuikEval System |
| 设计资源： | DC941A Design File DC941A Schematic |
| 标准包装： | 1 |
| 系列： | Easy Drive™, QuikEval™ |
| ADC 的数量： | 1 |
| 位数： | 16 |
| 采样率（每秒）： | 6.8 |
| 数据接口： | MICROWIRE?，串行，SPI? |
| 工作温度： | 0°C ~ 70°C |
| 已用 IC / 零件： | LTC2482 |
| 已供物品： | 板 |
| 相关产品： | LTC2482IDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#TRPBF-ND - IC ADC 16BIT 10-DFN LTC2482IDD#PBF-ND - IC ADC 16BIT 10-DFN LTC2482CDD#PBF-ND - IC ADC 16BIT 10-DFN |
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LTC2482
13
2482fc
APPLICATIONS INFORMATION
Conversion Clock
A major advantage the delta-sigma converter offers over
conventional type converters is an on-chip digital lter
(commonly implemented as a SINC or Comb lter). For
high resolution, low frequency applications, this lter is
typically designed to reject line frequencies of 50Hz or 60Hz
plus their harmonics. The lter rejection performance is
directly related to the accuracy of the converter system
clock. The LTC2482 incorporates a highly accurate on-chip
oscillator. This eliminates the need for external frequency
setting components such as crystals or oscillators.
Frequency Rejection Selection (fO)
The LTC2482 internal oscillator provides better than
87dB normal mode rejection at the line frequency and all
its harmonics (up to the 255th) for the frequency range
48Hz to 62.4Hz.
Whenafundamentalrejectionfrequencydifferentfrom50Hz/
60Hz is required, when more than 87dB rejection is needed
for 50Hz/60Hz, or when the converter must be synchronized
with an outside source, the LTC2482 can operate with an
external conversion clock. The converter automatically
detects the presence of an external clock signal at the fO pin
and turns off the internal oscillator. The frequency fEOSC of
the external signal must be at least 10kHz to be detected. The
external clock signal duty cycle is not signicant as long as
the minimum and maximum specications for the high and
low periods tHEO and tLEO are observed.
While operating with an external conversion clock of a
frequency fEOSC, the LTC2482 provides better than 110dB
normal mode rejection in a frequency range of fEOSC/5120
±4% and its harmonics. The normal mode rejection as a
DIFFERENTIAL INPUT SIGNAL FREQUENCY
DEVIATION FROM NOTCH FREQUENCY fEOSC/5120(%)
–12
–8
–4
0
4
8
12
NORMAL
MODE
REJECTION
(dB)
2480 F03
–80
–85
–90
–95
–100
–105
–110
–115
–120
–125
–130
–135
–140
Figure 3. LTC2482 Normal Mode Rejection When Using
an External Oscillator
function of the input frequency deviation from fEOSC/5120
is shown in Figure 3.
Whenever an external clock is not present at the fO pin, the
converter automatically activates its internal oscillator and
enters the internal conversion clock mode. The LTC2482
operation will not be disturbed if the change of conversion
clock source occurs during the sleep state or during the
data output state while the converter uses an external serial
clock. If the change occurs during the conversion state,
the result of the conversion in progress may be outside
specications but the following conversions will not be
affected. If the change occurs during the data output state
and the converter is in the Internal SCK mode, the serial
clock duty cycle may be affected but the serial data stream
will remain valid.
Table 3 summarizes the duration of each state and the
achievable output data rate as a function of fO.
Table 3. LTC2482 State Duration
STATE
OPERATING MODE
DURATION
CONVERT
Internal Oscillator
50Hz/60Hz Rejection
147ms, Output Data Rate ≤ 6.8 Readings/s
External Oscillator
fO = External Oscillator
with Frequency fEOSC kHz
(fEOSC/5120 Rejection)
41036/fEOSCs, Output Data Rate ≤ fEOSC/41036 Readings/s
SLEEP
As Long As CS = High, After a Conversion is Complete
DATA OUTPUT Internal Serial Clock
fO = Low/High
(Internal Oscillator)
As Long As CS = Low But Not Longer Than 0.62ms (24 SCK Cycles)
fO = External Oscillator with
Frequency fEOSC kHz
As Long As CS = Low But Not Longer Than 192/fEOSCms (24 SCK Cycles)
External Serial Clock with Frequency fSCK kHz
As Long As CS = Low But Not Longer Than 24/fSCKms (24 SCK Cycles)
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