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参数资料
型号： DEMO9S08JS16
厂商： Freescale Semiconductor
文件页数： 10/32页
文件大小： 0K
描述： BOARD DEMO FOR JS16 FAMILY
标准包装： 1
类型： MCU
适用于相关产品： MC9S08JS16
所含物品： 2 个板，线缆，文档，DVD
产品目录页面： 730 (CN2011-ZH PDF)
相关产品： MC9S08JS16CWJ-ND - IC MCU 8BIT 16K FLASH 20SOIC
MC9S08JS16CFK-ND - IC MCU 8BIT 16K FLASH 24QFN
MC9S08JS16 Series MCU Data Sheet, Rev. 4
Electrical Characteristics
Freescale Semiconductor
18
3.8
MCG Specifications
Table 9. MCG Frequency Specifications (Temperature Range = –40 to 85
°C Ambient)
Num C
Rating
Symbol
Min
Typical
Max
Unit
1
C Average internal reference frequency — untrimmed
fint_ut
25
32.7
41.66
kHz
2
P Average internal reference frequency — trimmed
fint_t
31.25
—
39.0625
kHz
3
T Internal reference startup time
tirefst
—60
100
μs
4
C DCO output frequency range — untrimmed
fdco_ut
25.6
33.48
42.66
MHz
5
P DCO output frequency range — trimmed
fdco_t
32
—
40
MHz
6C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature (using FTRIM)
Δf
dco_res_t
—
±0.1
±0.2
%fdco
7C
Resolution of trimmed DCO output frequency at
fixed voltage and temperature (not using FTRIM)
Δf
dco_res_t
—
±0.2
±0.4
%fdco
8P
Total deviation of trimmed DCO output frequency
over voltage and temperature
Δf
dco_t
—
0.5
–1.0
±2
%fdco
9C
Total deviation of trimmed DCO output frequency
over fixed voltage and temperature range of
0–70
°C
Δf
dco_t
—
±0.5
±1
%fdco
10
C FLL acquisition time1
1 This specification applies any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
tfll_acquire
——
1
ms
11
D PLL acquisition time2
2 This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled
(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it
is already running.
tpll_acquire
——
1
ms
12
C
Long term Jitter of DCO output clock (averaged over
2ms interval)3
CJitter
—0.02
0.2
%fdco
13
D VCO operating frequency
fvco
7.0
—
55.0
MHz
14
D PLL reference frequency range
fpll_ref
1.0
—
2.0
MHz
15
T
Long term accuracy of PLL output clock (averaged
over 2 ms)
fpll_jitter_2ms
—
0.5904
—%
16
T Jitter of PLL output clock measured over 625 ns5
fpll_jitter_625ns
—
0.5664
—%
17
D Lock entry frequency tolerance6
Dlock
±1.49
—
±2.98
%
18
D Lock exit frequency tolerance7
Dunl
±4.47
—
±5.97
%
19
D Lock time — FLL
tfll_lock
——
tfll_acquire+
1075(1/fint_t)
s
20
D Lock time — PLL
tpll_lock
——
tpll_acquire+
1075(1/fpll_ref)
s
21
D
Loss of external clock minimum frequency —
RANGE = 0
floc_low
(3/5) x fint
—
kHz
22
D
Loss of external clock minimum frequency —
RANGE = 1
floc_high
(16/5) x fint
—
kHz
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