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参数资料
| 型号： | DK-MAXII-1270N |
| 厂商： | Altera |
| 文件页数： | 29/38页 |
| 文件大小： | 0K |
| 描述： | KIT DEV MAXII W/EPM 1270N |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | MAX? II CPLD Development Kit |
| 标准包装： | 1 |
| 系列： | MAX® II |
| 类型： | CPLD |
| 适用于相关产品： | MAX?II CPLD |
| 所含物品： | 开发板、Quartus?II 网络版、Nios?II 网络版、缆线、附件、参考设计和演示 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | 544-2266-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-2265-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-1732-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1723-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1722-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1721-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1675-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-1652-ND - IC MAX II CPLD 1270 LE 144-TQFP 544-1388-ND - IC MAX II CPLD 1270 LE 144-TQFP 544-1387-ND - IC MAX II CPLD 1270 LE 144-TQFP 更多... |
| 其它名称： | 544-2380 |
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Getting Started
e.
Read the UFM —The UFM is arranged as 256 locations, each
containing 32 bits of data. Currently residing in the UFM is the
inverse of each address. Set the default encoding to
Hexadecimal and click Read UFM . The data displayed should
be FFFF FFFE FFFD FFFC FFFB and so forth. You can recompile
this design with a different memory initialization file (MIF) to
change the data in the UFM. Note that when you read from the
UFM, a file called UFMDataBack.txt is created in the same
directory where the USB_Utility.exe file resides. This file is
re-created each time you read the UFM. It contains the
addresses and the data read from those addresses.
1
UFMDataBack.txt must not be open when you read from
the UFM.
1
f.
Display the board temperature and push button counts —Press the
S2, S3, and S4 buttons on the board. Note that each time a
button is pressed, the corresponding text box on the GUI
increments. Also note that the board temperature is updated
each time a switch is pressed.
The SRAM and UFM read/write options only read or write
384 bytes at a time. This data is always written to or read from
the 384 lowest address locations.
Understanding the Functionality of the USB Reference Design
The USB Reference Design has two pieces:
■
■
Verilog code written to dictate the functionality of the MAX II device
Visual Basic code to control the PC application
The MAX II design consists entirely of state machines. Each individual
design file contains a state machine to control the reading/writing of each
component. These files contain extensive comments and designers are
encouraged to look through the Verilog code to gain a complete
understanding of how the MAX II design functions. The Director.v code
constantly awaits for one of two things to happen: either a button is
pressed or data arrives from the PC. If a button is pressed, the Director
enables the PassivesInterface.v , which takes over control of the output to
the USB MAC FIFO and writes the values of the Switch Counters and
Temperature blocks. If data is received from the PC, then the Director
passes control to the UFMInterface.v , the SRAMInterface.v, or the
LCDInterface.v , depending on the value of the data received. Refer to the
Verilog code itself for more details on the operation of this MAX II design.
Altera Corporation
July 2005
Development Kit Version 1.1.0 2–21
MAX II Development Kit Getting Started User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| DK-N2EVAL-3C25N | KIT DEV NIOS II CYCLONE III ED. |
| DK-NIOS-2C35N | NIOS II KIT W/CYCLONE II EP2C35N |
| DK-NIOS-2S60N | NIOS II KIT W/STRATIX II EP2S60N |
| DK-PCI-2C35N | PCI KIT W/CYCLONE II EP2C35N |
| DK-PCIE-2SGX90N | PCIE KIT W/S II GX EP2SGX90N |
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