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参数资料
| 型号： | DK-MAXII-1270N |
| 厂商： | Altera |
| 文件页数： | 33/38页 |
| 文件大小： | 0K |
| 描述： | KIT DEV MAXII W/EPM 1270N |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 特色产品： | MAX? II CPLD Development Kit |
| 标准包装： | 1 |
| 系列： | MAX® II |
| 类型： | CPLD |
| 适用于相关产品： | MAX?II CPLD |
| 所含物品： | 开发板、Quartus?II 网络版、Nios?II 网络版、缆线、附件、参考设计和演示 |
| 产品目录页面： | 605 (CN2011-ZH PDF) |
| 相关产品： | 544-2266-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-2265-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-1732-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1723-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1722-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1721-ND - IC MAX II CPLD 1270 LE 256-MBGA 544-1675-ND - IC MAX II CPLD 1270 LE 256-FBGA 544-1652-ND - IC MAX II CPLD 1270 LE 144-TQFP 544-1388-ND - IC MAX II CPLD 1270 LE 144-TQFP 544-1387-ND - IC MAX II CPLD 1270 LE 144-TQFP 更多... |
| 其它名称： | 544-2380 |
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Getting Started
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Start-up —When the MAX II device has been successfully
programmed, the Control block automatically accesses a section of
the UFM that prompts an introduction sequence to appear on the
LCD screen. This sequence loops indefinitely until a player presses
the Bet button to begin game play.
Bet Selection —The Bet button provides access to three separate
memory spaces within the UFM, representing the three fixed wager
amounts. Each time the button is pressed, a memory pointer cycles
to the next space in the sequence, displaying the corresponding
wager amount on the LCD screen. The Control block keeps track of
the memory pointer, and thus can cycle through the three wager
values repeatedly.
Spin Engagement —When the Spin button is toggled, the Control
block state machine is sent through a series of actions that affect the
final display of the LCD. First the LFSR is sampled and three
pseudo-random values are generated from its output. Based on the
commonality of these values, a new bankroll total is calculated and
stored internally. This total is then divided into three separate values
that represent the Hundreds, Tens, and Ones place of the number.
These values, along with the LSFR generated values for each reel, are
mapped to 11-bit codes that prompt the LCD to display the correct
number value.
When the values have been calculated and mapped, the Registers block
(see Figure 2–8 ) is updated with new bankroll and reel values. The block
then uses the MUX function to access the flash memory block (for
simulated spinning action of the reel), and the Register block (to display
the final bankroll and reel values). Upon completion of this process, the
design cycles back to monitor the status of the Bet signal to prepare for
another spin.
LCD Controller
The MAX II Slot Game Reference Design communicates with the
on-board LCD through a custom-built controller interface. The logic
block performs several functions vital to the game behavior. Upon
successful programming of the device, the block sequentially loads a
series of specific codes that initialize the LCD hardware and configure the
display environment. When initialization is complete, it interprets 11-bit
instructions fed by the design’s Control block, and manages the delivery
of characters to be displayed on the screen. Based on the value of the
11-bit input bus, the controller handles changes to the speed, content, and
direction (read/write) of LCD data.
Altera Corporation
July 2005
Development Kit Version 1.1.0 2–25
MAX II Development Kit Getting Started User Guide
相关PDF资料 |
PDF描述 |
|---|---|
| DK-N2EVAL-3C25N | KIT DEV NIOS II CYCLONE III ED. |
| DK-NIOS-2C35N | NIOS II KIT W/CYCLONE II EP2C35N |
| DK-NIOS-2S60N | NIOS II KIT W/STRATIX II EP2S60N |
| DK-PCI-2C35N | PCI KIT W/CYCLONE II EP2C35N |
| DK-PCIE-2SGX90N | PCIE KIT W/S II GX EP2SGX90N |
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