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参数资料
| 型号： | DK-PCI-2C35N |
| 厂商： | Altera |
| 文件页数： | 29/40页 |
| 文件大小： | 0K |
| 描述： | PCI KIT W/CYCLONE II EP2C35N |
| 标准包装： | 1 |
| 系列： | Cyclone® II |
| 类型： | FPGA：PCI 开发套件 |
| 适用于相关产品： | Cyclone ll 2C35N |
| 所含物品： | 开发板、Quartus?II 网络版、缆线、附件、参考设计和演示 |
| 相关产品： | 544-2115-ND - IC CYCLONE II FPGA 33K 484-UBGA 544-2114-ND - IC CYCLONE II FPGA 33K 484-UBGA 544-2113-ND - IC CYCLONE II FPGA 33K 484-UBGA 544-2112-ND - IC CYCLONE II FPGA 33K 484-UBGA 544-2111-ND - IC CYCLONE II FPGA 33K 672-FBGA 544-2110-ND - IC CYCLONE II FPGA 33K 672-FBGA 544-2109-ND - IC CYCLONE II FPGA 33K 484-FBGA 544-2108-ND - IC CYCLONE II FPGA 33K 484-FBGA 544-1694-ND - IC CYCLONE II FPGA 33K 672-FBGA 544-1693-ND - IC CYCLONE II FPGA 33K 672-FBGA 更多... |
| 其它名称： | 544-1733 |
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Getting Started
f
To simulate your design using this walkthrough, you need the Model
Technology ModelSim simulator version 6.0 or later, which is not
included with the kit.
1
The reference design’s DDR2 memory simulation model is only
available in Verilog HDL, and the reference design is in VHDL.
Mixed VHDL and Verilog HDL simulation may require
additional ModelSim licenses.
Prototyping Walkthrough Files
The prototyping walkthrough uses reference design source files,
simulation files, and compilation files that you copy from the PCI
Development Kit, Cyclone II Edition CD-ROM installation directory to your
working directory.
Table 2–2 describes the reference design source files used in the
walkthrough. These files are located in the < path > \cycloneii_pci_kit-
v1.0.0\reference_design\vhdl directory.
Table 2–2. Prototyping Walkthrough Reference Design Source Files (Part 1 of 2)
File
cpd_top.vhd
Subdirectory
(1)
—
Description
The top-level file that instantiates the PCI and DDR2 SDRAM cores
and the local design. Refer to AN 390: PCI-to-DDR2 SDRAM
Reference Design for a description of the local design.
vhdl_components.vhd —
The VHDL component instantiation templates.
pci_top.vhd
backend.vhd
pci_mt64
pci_local
This wrapper file implements the pci_mt64 core. The file was
generated with the PCI Compiler wizard and the following settings:
VHDL output file
●
64-bit master/target MegaCore function ( pci_mt64 )
●
Device ID is set to 0x0009
●
Revision ID is set to 0x1
●
Subsystem ID is set to 0xE102
●
Subsys Vendor ID is set to 0x1172
●
BAR0 is a 1-MByte memory
●
BAR1 is a 64-MByte prefetchable memory
●
All other parameters are at the default values
●
For more information, refer to the PCI Compiler User Guide .
The top level of the local PCI interface.
Altera Corporation
Core Version a.b.c variable
2–19
May 2005
PCI Development Kit, Cyclone II Edition Getting Started User Guide
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