参数资料
型号: DK-PCI-2C35N
厂商: Altera
文件页数: 38/40页
文件大小: 0K
描述: PCI KIT W/CYCLONE II EP2C35N
标准包装: 1
系列: Cyclone® II
类型: FPGA:PCI 开发套件
适用于相关产品: Cyclone ll 2C35N
所含物品: 开发板、Quartus?II 网络版、缆线、附件、参考设计和演示
相关产品: 544-2115-ND - IC CYCLONE II FPGA 33K 484-UBGA
544-2114-ND - IC CYCLONE II FPGA 33K 484-UBGA
544-2113-ND - IC CYCLONE II FPGA 33K 484-UBGA
544-2112-ND - IC CYCLONE II FPGA 33K 484-UBGA
544-2111-ND - IC CYCLONE II FPGA 33K 672-FBGA
544-2110-ND - IC CYCLONE II FPGA 33K 672-FBGA
544-2109-ND - IC CYCLONE II FPGA 33K 484-FBGA
544-2108-ND - IC CYCLONE II FPGA 33K 484-FBGA
544-1694-ND - IC CYCLONE II FPGA 33K 672-FBGA
544-1693-ND - IC CYCLONE II FPGA 33K 672-FBGA
更多...
其它名称: 544-1733
Using the Board as a Prototyping Platform
1
To ensure that the prototype pin assignments match the board’s
pin assignments, you should use the provided constraint file
( cpd_top.qsf ) for pin-out reference. Unless otherwise indicated,
you should assume that constraint files not shipped with the kit
contain different pin assignments from that required by the
board.
For this walkthrough, the steps are omitted and you use the provided
ready-to-use constraint files cpd_top.qsf in the
c: pci_prototype_example\QuartusII directory.
1
The kit’s constraint file ( .qsf ) is made for the PCI Compiler
version 4.0.0 and the DDR & DDR2 SDRAM Controller
Compiler version 3.2.0 using the Quartus II software
version 5.0; therefore, the constraint files should be used
with the same MegaCore function and software versions. If
you use a different MegaCore function or software version,
you may experience timing violations or compilation
errors.
9.
Choose Start Compilation (Processing menu) to synthesize and
compile the project and generate the cpd_top.sof and cdp_top.pof
files.
If you do not have licenses for the pci_mt64 MegaCore function or
the DDR & DDR2 SDRAM Controller Compiler, you will not be able
to generate unrestricted programming files. In this case, use the file
cpd_top.pof from your working directory to complete the steps in
this walkthrough.
10. Choose Compilation Report (Processing menu) and expand the
Timing Analyzer section to check the timing of your compiled
design.
11. Choose Compilation Report (Processing menu) and select Pin-Out
File to make sure all of your pins are assigned properly.
Configure Your Cyclone II Device
You can configure the Cyclone II device using either the SOF or POF
created in the previous section via the JTAG interface or by programming
the on-board serial flash memory. Follow the steps outlined in
preferred configuration method. The next step in this walkthrough
assumes that you have programmed your POF into the serial flash
memory and you are ready to test your new configuration in hardware.
2–28
Core Version a.b.c variable
Altera Corporation
PCI Development Kit, Cyclone II Edition Getting Started User Guide
May 2005
相关PDF资料
PDF描述
DK-PCIE-2SGX90N PCIE KIT W/S II GX EP2SGX90N
DK-SI-2SGX90N SI KIT W/SII GX EP2SGX90N
DK-SI-4SGX230N KIT DEV STRATIX IV 4SGX230N/C2
DK-START-3C25N KIT STARTER CYCLONE III EP3C25
DK-START-4CGX15N KIT STARTER CYCLONE IV GX
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