参数资料
| 型号： | DLP-HS-FPGA3 |
| 厂商： | DLP Design Inc |
| 文件页数： | 18/18页 |
| 文件大小： | 0K |
| 描述： | MODULE USB-TO-FPGA SPARTAN 3A |
| 标准包装： | 1 |
| 系列： | FPGA |
| 模块/板类型： | FPGA 模块 |
| 适用于相关产品： | USB |
| 其它名称： | 813-1036 |
Rev. 1.1 (April 2012)
9
DLP Design, Inc.
Command Packets
Command
Packet
Description
Byte
Hex
Value
Return/Comments
Ping
Issues Ping
0
0x00
Ping Command - 0x56 will be returned indicating that
the DLP-HS-FPGA3 is found on the selected port.
Read
Version/
Status
Accesses
the internal
version/
status
registers
0
0x10
Read Version/Status Registers Command
1
0xnn
Register Address: 0xnn =
0x00 = Board ID (0x30 = Production PCB)
0x01 = FPGA Type ID : 0x6A = XC3S1400A
0x02 = Design Version ID 1 (Design Month)
0x03 = Design Version ID 2 (Design Day)
0x04 = Design Version ID 3 (Design Year)
0x05 = Design Version ID 4 (Design Version)
0x06 = DDR2 Status: 0x00 = Not Initialized
0x01 = Initialized
Loopback
Returns the
data byte
received
0
0x20
Loopback Command
1
0xnn
The byte sent to the DLP-HS-FPGA3 (0xnn) will be
returned back.
Loopback
Compliment
Returns the
compliment
of data byte
received
0
0x21
Loopback Compliment Command
1
0xnn
The byte sent to the DLP-HS-FPGA3 (0xnn) will be
complimented and returned back.
Read Pin
Reads the
state of one
of the user
I/O pins
0
0x30
Read Pin Command
1
0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is read and returns:
0x00 = User I/O pin 0xnn is low
0x01 = User I/O pin 0xnn is high
Clear Pin
Forces the
selected
user I/O pin
low
0
0x40
Clear Pin Command
1
0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is cleared. The specified user I/O
number is returned.
Set Pin
Forces the
selected
user I/O pin
high
0
0x41
Set Pin Command
1
0x00
–
0x3E
The user I/O pin numbers are described in Table 2.
User I/O pin 0xnn is set. The specified user I/O number
is returned.
Initialize
Memory
Initializes
DDR2
SDRAM
0
0x70
The Initialize Memory Command configures the DDR2
SDRAM for access by the FPGA. The memory cannot
be accessed without being initialized.
IMPORTANT NOTE ON DDR2 SDRAM DATA ACCESS:
Writes and reads made to and from the DDR2 SDRAM using the reference design on the
DLP-HS-FPGA3 module are always performed 4 bytes at a time due to the fact that the device is
configured for a burst length of four. What this means is that Column Address Bits 0 and 1 only
change the order of the read or write bytes; they still refer to the same 4 bytes. Therefore, to
increment the DDR2 SDRAM address for consecutive memory locations, the column address must be
incremented by 4.
Incrementing the column address by anything less than 4 simply changes the order in which the 4
bytes specified by Column Address 9:3 are written to the memory or returned to the user.
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| DLP-HS-FPGA-A | 功能描述:FPGA Embedded Module Spartan-3A, XC3S200A FT2232H 66MHz 32MB 制造商:dlp design inc. 系列:FPGA 零件状态:有效 模块/板类型:FPGA，USB ?? 核心处理器:Spartan-3A，XC3S200A 协处理器:FT2232H 速度:66MHz 闪存大小:- RAM 容量:32Mb 连接器类型:USB - B，引脚接头 大小/尺寸:3" x 1.2"（76.2mm x 30.5mm） 工作温度:0°C ~ 70°C 标准包装:1 |
| DLP-IO14 | 功能描述:数据记录与采集 14-Channel Data-Acq Module RoHS:否 制造商:Lantronix 描述/功能:Analog device server 显示器类型:None 电流额定值: |
| DLP-IO16 | 功能描述:界面模块 USB/Micro Dev Board RoHS:否 制造商:4D Systems 产品:Serial Converters 通道/端口数量: 数据速率: 接口类型:USB, UART 工作电源电压:3.3 V, 5 V 最大工作温度: |
| DLP-IO20 | 功能描述:数据记录与采集 USB-BASED 20-CHANNEL DATA ACQUISITION MOD RoHS:否 制造商:Lantronix 描述/功能:Analog device server 显示器类型:None 电流额定值: |
| DLP-IO26 | 功能描述:开发板和工具包 - PIC / DSPIC USB/Micro Dev Board RoHS:否 制造商:Microchip Technology 产品:Starter Kits 工具用于评估:chipKIT 核心:Uno32 接口类型: 工作电源电压: |
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