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参数资料
| 型号： | DR-TRC105-315-EV |
| 厂商： | RFM |
| 文件页数： | 23/67页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 315MHZ RFM RFIC |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 频率： | 310MHz ~ 319.5MHz |
| 适用于相关产品： | TRC105 |
| 已供物品： | 2 个板，天线，电池 |
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When receive mode is enabled, the demodulator detects the preamble followed by the start pattern. If fixed length
packet format is enabled, then the number of bytes received as the payload is given by the PKTCFG1C_Pkt_
len[6..0] parameter. In variable length and extended variable length packet modes, the first byte received after
the start pattern is interpreted as the length of the balance of the payload. An internal length counter is initialized
to this length. The PKTCFG1C_Pkt_len[6..0] register must be set to a value which is equal to or greater than the
maximum expected length byte value of the received packet. If the length byte value of a received packet is
greater than the value in the PKTCFG1C_ Pkt_len[6..0] register, the packet is discarded. Otherwise the packet
payload begins loading into the FIFO.
If address match is enabled, the second byte received in a variable length mode or the first byte in the fixed length
mode is interpreted as the node address. If this address matches the byte in PKTCFG1D_Node_Addrs[7..0] ,
reception of the packet continues, otherwise it is stopped. A CRC check is performed if PKTCFG1E_CRC_
En[3] is set to 1. If the CRC check is successful, a 1 is loaded in the PKTCFG1E_CRC_stat[0] bit, and CRC_OK
and Dat_Rdy interrupts are simultaneously generated on IRQ1 and IRQ0 respectively. This signals that the pay-
load or balance of the payload can be read from the FIFO. In receive mode, address match, Dat_Rdy, and
CRC_OK interrupts and the CRC_stat bit are reset when the last byte in the FIFO is read. Note the FIFO can be
read in standby mode by setting PGCFG1F_ RnW_FIFO[6] bit to 1. In standby, reading the last FIFO byte does
not clear CRC_OK and the CRC_stat bit. They are reset once the TRC103 is put in receive mode again and a
start pattern is detected.
If the CRC check fails, the FIFO is cleared and no interrupts are generated. This action can be overridden by set-
ting PGCFG1F_CRCclr_auto[7 ] to 1, which forces a Data_Rdy interrupt and preserves the payload in the FIFO
even if the CRC fails.
If address checking is enabled, the second byte received in a variable length mode or the first byte in the fixed
length mode is interpreted as the node address. If this address matches the byte in PKTCFG1D_Node_
Addrs[7..0] , reception of the packet continues, otherwise it is stopped. A CRC check is performed if PKTCFG1E_
CRC_En[3] is set to 1. If the CRC check is successful, a 1 is loaded in the PKTCFG1E_CRC_stat[0] bit, and
CRC_OK and Dat_Rdy interrupts are simultaneously generated on IRQ1 and IRQ0 respectively, signaling the
payload or balance of the payload can be read from the FIFO. Note the FIFO can be read in standby mode by
setting PGCFG1F_ RnW_FIFO[6] bit to 1. If the CRC check fails, the FIFO is cleared and no interrupts are gen-
erated. This action can be overridden by setting PGCFG1F_CRCclr_auto[7 ] to 1, which forces a Data_Rdy inter-
rupt and preserves the payload in the FIFO even if the CRC fails.
3.9.5 Packet Filtering
Received packets can be filtered based on two criteria: length filtering and address filtering. In variable length or
extended variable length packet formats, PKTCFG1C_Pkt_len[6..0] stores the maximum packet length permitted.
If the received packet length is greater than this value, then the packet is discarded. Node address filtering is en-
abled by setting parameter PKTCFG1E_Addrs_cmp[2..1] to any value other than 00, i.e., 01, 10 or 11. These
settings enable the following three options:
PKTCFG1E_Addrs_cmp[2..1] = 01: This configuration activates the address filtering function on the packet
handler and the received address byte is compared with the address in the PKTCFG1D_Node_Addrs[7..0] regis-
ter. If both address bytes are the same, the received packet is for the current destination and is stored in FIFO.
Otherwise it is discarded. An interrupt can also be generated on IRQ0 if the address comparison is successful.
PKTCFG1E_Addrs_cmp[2..1] = 10: In this configuration the received address is compared to both the
PKTCFG1D_Node_Addrs[7..0] register and constant 0x00. If the received address byte matches either value,
the packet is accepted. An interrupt can also be generated on IRQ0 if the address comparison is successful. The
0x00 address is useful for sending broadcast packets.
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Page 23 of 67
TRC105 - 05/29/13
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DR-TRC105-345-DK | 功能描述:射频开发工具 TRC105 Development Kit 342-348 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| DR-TRC105-345-EV | 功能描述:射频开发工具 TRC105 Evaluation Board 342-348 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| DR-TRC105-372-DK | 功能描述:射频开发工具 TRC105 Development Kit 365-381 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| DR-TRC105-372-EV | 功能描述:射频开发工具 TRC105 Evaluation Board 365-381 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
| DR-TRC105-390-DK | 功能描述:射频开发工具 TRC105 Development Kit 382-398 MHz RoHS:否 制造商:Taiyo Yuden 产品:Wireless Modules 类型:Wireless Audio 工具用于评估:WYSAAVDX7 频率: 工作电源电压:3.4 V to 5.5 V |
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