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参数资料
| 型号： | DS1225AB |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | DRAM |
| 英文描述： | 64K Nonvolatile SRAM(64K非易失性静态RAM) |
| 中文描述： | 8K X 8 NON-VOLATILE SRAM MODULE, 200 ns, PDIP28 |
| 文件页数： | 2/9页 |
| 文件大小： | 91K |
| 代理商： | DS1225AB |
DS1225AB/AD
021998 2/9
READ MODE
The DS1225AB and DS1225AD execute a read cycle
whenever WE (Write Enable) is inactive (high) and CE
(Chip Enable) and OE (Output Enable) are active (low).
The unique address specified by the 13 address inputs
(A
0
–A
12
) defines which of the 8192 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
access times are also satisfied. If CE and OE access
times are not satisfied, then data access must be mea-
sured from the later occurring signal and the limiting pa-
rameter is either t
CO
for CE or t
OE
for OE rather than ad-
dress access.
WRITE MODE
The DS1225AB and DS1225AD execute a write cycle
whenever the WE and CE signals are active (low) after
address inputs are stable. The latter occurring falling
edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (t
WR
) before another
cycle can be initiated. The OE control signal should be
kept inactive (high) during write cycles to avoid bus con-
tention. However, if the output drivers are enabled (CE
and OE active) then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1225AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1225AD provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below ap-
proximately 3.0 volts, the power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
4.75 volts for the DS1225AB and 4.5 volts for the
DS1225AD.
FRESHNESS SEAL
Each DS1225 is shipped from Dallas Semiconductor
with the lithium energy source disconnected, guaran-
teeing full energy capacity. When V
CC
is first applied at
a level of greater than V
TP
, the lithium energy source is
enabled for battery backup operation.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1225AD | 16K Nonvolatile SRAM(64K非易失性SRAM) |
| DS1225Y | 64K Nonvolatile SRAM(64K 非易失性静态RAM) |
| DS1230AB(中文) | 256K NV SRAM(256K非易失性SRAM) |
| DS1230W | 3.3V 256K Nonvolatile SRAM(3.3V 256K 非易失性静态RAM) |
| DS1230Y | 256K Nonvolatile SRAM(256K 非易失性静态RAM) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1225AB/AD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:64k Nonvolatile SRAM |
| DS1225AB-150 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1225AB-150+ | 功能描述:NVRAM 64k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1225AB-150IND | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1225AB-150-IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:64k Nonvolatile SRAM |
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