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参数资料
| 型号： | DS1308U-33+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC RTC 56BYTE NVRAM I2C 8UMAX |
| 标准包装： | 3,000 |
| 类型： | 时钟/日历 |
| 特点： | 闰年，NVSRAM，方波输出 |
| 存储容量： | 56B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | I²C，2 线串口 |
| 电源电压： | 3 V ~ 5.5 V |
| 电压 - 电源，电池： | 1.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
DS1308
Low-Current I2C RTC with 56-Byte NV RAM
11
Maxim Integrated
Control Register (07h)
The control register controls the operation of the SQW/CLKIN pin and provides oscillator status.
Bit 7: Output Control (OUT). Controls the output level of the SQW/CLKIN pin when the square-wave output is disabled
and VCC>VPF. If SQWE = 0, the logic level on the SQW/CLKIN pin is 1 if OUT = 1; it is 0 if OUT = 0. See Table 4.
Bit 6: Enable Clock Input (ECLK). This bit controls the direction of the SQW/CLKIN pin (see Table 4). When ECLK = 1,
the SQW/CLKIN pin is an input, with the expected input rate defined by the states of RS1 and RS0. When ECLK = 0, the
SQW/CLKIN pin is an output, with the square-wave frequency defined by the states of RS1 and RS0.
Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some
time period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set
to logic 1 when the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition.
The following are examples of conditions that may cause the OSF bit to be set:
The first time power is applied.
The voltage present on VCC and VBAT are insufficient to support oscillation.
The CH bit is set to 1, disabling the oscillator.
External influences on the crystal (i.e., noise, leakage, etc.).
This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1
leaves the value unchanged.
Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either
VCC or VBAT applied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.
Bit 3: Loss of Signal (LOS). This status bit indicates the state of the CLKIN pin. The LOS bit is set to 1 when the RTC
counter is no longer conditioned by the external clock. This occurs when 1) ECLK = 0, or 2) when the CLKIN input signal
stops toggling, or 3) when the CLKIN frequency differs by more than Q0.8% from the selected input frequency. This bit
remains a 1 until written to 0. Attempting to write LOS = 1 leaves the value unchanged. Clearing the LOS flag when the
CLKIN frequency is invalid inhibits subsequent detections of the input frequency deviation.
Bit 2: Battery Backup Clock (BBCLK). When set to logic 1, this bit enables the SQW/CLKIN I/O while the part is pow-
ered by VBAT. When set to logic 0, this bit disables the SQW/CLKIN I/O while the part is powered by VBAT.
Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the SQW/CLKIN output when the square-
wave has been enabled (SQWE = 1). Table 4 lists the square-wave frequencies that can be selected with the RS bits.
Table 4. SQW/CLKIN Pin Functions
X = Don’t care.
Bit #
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Name
OUT
ECLK
OSF
SQWE
LOS
BBCLK
RS1
RS0
POR
1
0
1
OUT
ECLK
SQWE
RS1
RS0
SQW/CLKIN
X
0
1
0
1Hz output
X
0
1
0
1
4.096kHz output
X
0
1
0
8.192kHz output
X
0
1
32.768kHz output
0
X
0
1
0
X
1
X
1
X
0
1Hz input
X
1
X
0
1
50Hz input
X
1
X
1
0
60Hz input
X
1
X
1
32.768kHz input
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