参数资料
型号: DS1337U/T&R
厂商: Maxim Integrated Products
文件页数: 10/16页
文件大小: 0K
描述: IC RTC SERIAL 2WIRE LP 8-USOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 3,000
类型: 时钟/日历
特点: 警报器,闰年,方波输出,涓流充电器
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
电压 - 电源,电池: 1.3 V ~ 1.8 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 8-TSSOP,8-MSOP(0.118",3.00mm 宽)
供应商设备封装: 8-uMAX
包装: 带卷 (TR)
DS1337 I
2C Serial Real-Time Clock
AC ELECTRICAL CHARACTERISTICS
(VCC = 1.8V to 5.5V, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Fast mode
100
400
SCL Clock Frequency
fSCL
Standard mode
0
100
kHz
Fast mode
1.3
Bus Free Time Between a
STOP and START Condition
tBUF
Standard mode
4.7
s
Fast mode
0.6
Hold Time (Repeated)
START Condition (Note 10)
tHD:STA
Standard mode
4.0
s
Fast mode
1.3
LOW Period of SCL Clock
tLOW
Standard mode
4.7
s
Fast mode
0.6
HIGH Period of SCL Clock
tHIGH
Standard mode
4.0
s
Fast mode
0.6
Setup Time for a Repeated
START Condition
tSU:STA
Standard mode
4.7
s
Fast mode
0
0.9
Data Hold Time
(Notes 11, 12)
tHD:DAT
Standard mode
0
s
Fast mode
100
Data Setup Time (Note 13)
tSU:DAT
Standard mode
250
ns
Fast mode
20 + 0.1CB
300
Rise Time of Both SDA and
SCL Signals (Note 14)
tR
Standard mode
20 + 0.1CB
1000
ns
Fast mode
20 + 0.1CB
300
Fall Time of Both SDA and
SCL Signals (Note 14)
tF
Standard mode
20 + 0.1CB
300
ns
Fast mode
0.6
Setup Time for STOP
Condition
tSU:STO
Standard mode
4.0
s
Capacitive Load for Each Bus
Line
CB
(Note 14)
400
pF
I/O Capacitance (SDA, SCL)
CI/O
(Note 15)
10
pF
Oscillator Stop Flag (OSF)
Delay
tOSF
100
ms
Note 1:
Limits at -40°C are guaranteed by design and are not production tested.
Note 2:
SCL only.
Note 3:
SDA,
INTA, and SQW/INTB.
Note 4:
ICCA—SCL clocking at max frequency = 400kHz, VIL = 0.0V, VIH = VCC.
Note 5:
Specified with the I
2C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6:
SQW enabled.
Note 7:
Specified with the SQW function disabled by setting INTCN = 1.
Note 8:
Using recommended crystal on X1 and X2.
Note 9:
The device is fully accessible when 1.8
VCC 5.5V. Time and date are maintained when 1.3V VCC 1.8V.
Note 10:
After this period, the first clock pulse is generated
Note 11:
A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 12:
The maximum tHD:DAT need only be met if the device does not stretch the LOW period (tLOW) of the SCL signal.
Note 13:
A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT to 250ns must then be met. This is
automatically the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR max + tSU:DAT = 1000 + 250 = 1250ns before the SCL
line is released.
Note 14:
CB—total capacitance of one bus line in pF.
Note 15:
Guaranteed by design. Not production tested.
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