参数资料
| 型号： | DS1347T+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/17页 |
| 文件大小： | 0K |
| 描述： | IC RTC/CALENDAR SPI 8TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 类型： | 时钟/日历 |
| 特点： | 警报器，闰年，SRAM |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | SPI |
| 电源电压： | 2 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN EP |
| 包装： | 标准包装 |
| 其它名称： | DS1347T+T&RDKR |
Low-Current, SPI-Compatible
Real-Time Clock
Maxim Integrated
7
DS1347
Detailed Description
The DS1347 is a real-time clock/calendar with an SPI-
compatible interface and 31 x 8 bits of SRAM. It pro-
vides seconds, minutes, hours, day of the week, date of
the month, month, and year information, held in seven
8-bit timekeeping registers (see the
Functional
Diagram). An on-chip 32.768kHz oscillator circuit
requires only a single external crystal to operate. Table
1 shows the device’s register addresses and defini-
tions. Time and calendar data are stored in the regis-
ters in binary-coded decimal (BCD) format. A polled
alarm function is included for scheduled timing of user-
defined times or intervals.
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
FUNCTION
RANGE
01h
0
10 SECONDS
SECONDS
Seconds
00–59
03h
ALM
OUT
10 MINUTES
MINUTES
Minutes
00–59
AM/PM
05h
12/
24
0
20 HR
10 HR
HOUR
Hours
1–12+
AM/PM
00–23
07h
0
10 DATE
DATE
Date
01–31
09h
0
10 MO
MONTH
Month
01–12
0Bh
0
DAY
Day
1–7
0Dh
10 YEAR
YEAR
Year
00–99
0Fh
WP
0
ID
Control
00h or 81h
13h
1000 YEAR
100 YEAR
Century
00–99
15h
0
YEAR
DAY
MONTH
DATE
HOUR
MINUTE SECOND
Alarm
Configuration
00h–7Fh
17h
EOSC
DOSF
EGFIL
0
OSF
1
Status
03h–E7h
19h
0
10 SECONDS
SECONDS
Alarm Seconds
00–59
1Bh
0
10 MINUTES
MINUTES
Alarm Minutes
00–59
AM/PM
1Dh
12/
24
0
20 HR
10 HR
HOURS
Alarm Hours
1–12 +
AM/PM
00–23
1Fh
0
10 DATE
DATE
Alarm Date
1–31
21h
0
10 MO
MONTH
Alarm Month
1–12
23h
0
DAY
Alarm Day
1–7
25h
10 YEAR
YEAR
Alarm Year
00–99
3Fh
See the Data Input (Burst Write) section.
Clock Burst
—
41h
X
RAM 0
00h–FFh
43h
X
RAM 1
00h–FFh
45h
X
RAM 2
00h–FFh
47h
X
RAM 3
00h–FFh
49h
X
RAM 4
00h–FFh
4Bh
X
RAM 5
00h–FFh
4Dh
X
RAM 6
00h–FFh
4Fh
X
RAM 7
00h–FFh
51h
X
RAM 8
00h–FFh
53h
X
RAM 9
00h–FFh
55h
X
RAM 10
00h–FFh
Table 1. Register Map
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