- 您现在的位置：买卖IC网 > PDF目录381719 > DS1350AB (MAXIM INTEGRATED PRODUCTS INC) 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的 4096K非易失性SRAM) PDF资料下载
参数资料
| 型号： | DS1350AB |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | DRAM |
| 英文描述： | 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的 4096K非易失性SRAM) |
| 中文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| 文件页数： | 2/11页 |
| 文件大小： | 114K |
| 代理商： | DS1350AB |
DS1350Y/AB
042398 2/11
READ MODE
The DS1350 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip
Enable) and OE (Output Enable) are active (low). The
unique address specified by the 19 address inputs (A
0
-
A
18
) defines which of the 524,288 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1350 devices excute a write cycle whenever the
WE and CE signals are in the active (low) state after
address inputs are stable. The later occurring falling
edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising
edge of CE or WE. All address inputs must be kept valid
throughout the write cycle. WE must return to the high
state for a minimum recovery time (t
WR
) before another
cycle can be initiated. The OE control signal should be
kept inactive (high) during write cycles to avoid bus con-
tention. However, if the output drivers are enabled (CE
and OE active) then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1350AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1350Y provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below
approximately 2.7 volts, the power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
2.7 volts, the power switching circuit connects external
V
CC
to the RAM and disconnects the lithium energy
source. Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1350AB and 4.5 volts for
the DS1350Y.
SYSTEM POWER MONITORING
DS1350 devices have the ability to monitor the external
V
CC
power supply. When an out–of–tolerance power
supply condition is detected, the NV SRAMs warn a pro-
cessor–based system of impending power failure by
asserting RST. On power up, RST is held active for 200
ms nominal to prevent system operation during pow-
er–on transients and to allow t
REC
to elapse. RST has
an open–drain output driver.
BATTERY MONITORING
The DS1350 devices automatically perform periodic
battery voltage monitoring on a 24 hour time interval.
Such monitoring begins within t
REC
after V
CC
rises
above V
TP
and is suspended when power failure
occurs.
After each 24 hour period has elapsed, the battery is
connected to an internal 1M
test resistor for one
second. During this one second, if battery voltage falls
below the battery voltage trip point (2.6V), the battery
warning output BW is asserted. Once asserted, BW
remains active until the module is replaced. The battery
is still retested after each V
CC
power–up, however, even
if BW is active. If the battery voltage is found to be higher
than 2.6V during such testing, BW is de–asserted and
regular 24–hour testing resumes. BW has an open–
drain output driver.
FRESHNESS SEAL
Each DS1350 is shipped from Dallas Semiconductor
with its lithium energy source disconnected, guarantee-
ing full energy capacity. When V
CC
is first applied at a
level greater than V
TP
, the lithium energy source is
enabled for battery backup operation.
PACKAGES
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC Pow-
erCap. The PowerCap Module package design allows
a DS1350 PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1350 PCM is
reflow soldered, a DS9034PC is snapped on top of the
PCM to form a complete Nonvolatile SRAM module.
The DS9034PC is keyed to prevent improper attach-
ment. DS1350 PowerCap Modules and DS9034PC
PowerCaps are ordered separately and shipped in sep-
arate containers. See the DS9034PC data sheet for fur-
ther information.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1350Y | 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的4096K非易失性SRAM) |
| DS1350W | 3.3V 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的3.3V 4096K非易失性SRAM) |
| DS1371 | 2-Wire, 32-Bit Binary Counter Watchdog Clock |
| DS1371U | 2-Wire, 32-Bit Binary Counter Watchdog Clock |
| DS1372 | I2C, 32-Bit, Binary Counter Clock with 64-Bit ID |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1350AB-100 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350AB-70 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350ABL-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1350ABL-100-IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1350ABL-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
发布紧急采购，3分钟左右您将得到回复。