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参数资料
| 型号： | DS1350AB |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | DRAM |
| 英文描述： | 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的 4096K非易失性SRAM) |
| 中文描述： | 512K X 8 NON-VOLATILE SRAM MODULE, 70 ns, DMA34 |
| 文件页数： | 7/11页 |
| 文件大小： | 114K |
| 代理商： | DS1350AB |
DS1350Y/AB
042398 7/11
POWER–DOWN/POWER–UP TIMING
(t
A
: See Note 10)
UNITS
PARAMETER
SYMBOL
MIN
TYP
MAX
NOTES
V
Fail Detect to CE and WE
Inactive
t
PD
1.5
μ
s
11
V
CC
slew from V
TP
to 0V
t
F
150
μ
s
V
CC
Fail Detect to RST Active
t
RPD
15
μ
s
14
V
CC
slew from 0V to V
TP
t
R
150
μ
s
V
Valid to CE and WE
Inactive
t
PU
2
ms
V
CC
Valid to End of Write
Protection
t
REC
125
ms
V
CC
Valid to RST Inactive
t
RPU
150
200
350
ms
14
V
CC
Valid to BW Valid
t
BPU
1
s
14
BATTERY WARNING TIMING
PARAMETER
Battery Test Cycle
(t
A
: See Note 10)
UNITS
hr
SYMBOL
t
BTC
t
BTPW
t
BW
MIN
TYP
24
MAX
NOTES
Battery Test Pulse Width
1
s
Battery Test to BW Active
1
s
(t
A
= 25
°
C)
NOTES
9
PARAMETER
Expected Data Retention Time
SYMBOL
t
DR
MIN
10
TYP
MAX
UNITS
years
WARNING:
Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode.
NOTES:
1. WE is high for a Read Cycle.
2. OE = V
IH
or V
IL
. If OE = V
IH
during write cycle, the output buffers remain in a high impedance state.
3. t
WP
is specified as the logical AND of CE and WE. t
WP
is measured from the latter of CE or WE going low to the
earlier of CE or WE going high.
4. t
DS
is measured from the earlier of CE or WE going high.
5. These parameters are sampled with a 5 pF load and are not 100% tested.
6. If the CE low transition occurs simultaneously with or latter than the WE low transition, the output buffers remain
in a high impedance state during this period.
7. If the CE high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain
in high impedance state during this period.
8. If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition, the output buffers
remain in a high impedance state during this period.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1350Y | 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的4096K非易失性SRAM) |
| DS1350W | 3.3V 4096K Nonvolatile SRAM with Battery Monitor(带电池监控的3.3V 4096K非易失性SRAM) |
| DS1371 | 2-Wire, 32-Bit Binary Counter Watchdog Clock |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1350AB-100 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350AB-70 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:4096k Nonvolatile SRAM with Battery Monitor |
| DS1350ABL-100 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1350ABL-100-IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1350ABL-70 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
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