DS1501/DS1511
071098 6/22
TABLE 2 LEGEND (DS1501/DS1511 REGISTER MAP):
0=“0” and are read only
PRS=PAB Reset Select bit
BME=Burst Mode Enable bit
EOSC=Oscillator start/stop bit
PAB=Power Active Bar control bit
TPE=Time of day/date alarm Power Enable bit
E32K=Enable 32.768 KHz output bit
TDF=Time of Day/Date alarm Flag
TIE=Time of Day/Date alarm Interrupt Enable bit
BB32=Battery Backup 32 kHz enable bit
KSF=Kickstart Flag
AM1–AM4=Alarm Mask bits
WDF=Watchdog Flag
KIE=Kickstart Interrupt Enable bit
DY/DT=Day/Date bit
IRQF=Interrupt Request Flag
WDE=Watchdog Enable bit
VRT1=Valid RAM and Time bit
TE=Transfer Enable bit
WDS=Watchdog Steering bit
VRT2=Auxiliary battery low bit
CS=Crystal Select bit
NOTE:
Unless otherwise specified, the state of the control/RTC/SRAM bits in the DS1501/DS1511 is not defined
upon initial power application; the DS1501/DS1511 should be properly configured/defined during initial configuration.
CLOCK OSCILLATOR CONTROL
The Clock oscillator may be stopped at any time. To
increase the shelf life of a backup lithium battery source,
the oscillator can be turned off to minimize current drain
from the battery. The EOSC bit is the MSB of the month
register (B7 of 05h). Setting it to a “1” stops the oscilla-
tor, setting to a “0” starts the oscillator.
READING THE CLOCK
When reading the RTC data, it is recommended to halt
updates to the external set of double buffered RTC reg-
isters. This puts the external registers into a static state
allowing data to be read without register values chang-
ing during the read process. Normal updates to the
internal registers continue while in this state. External
updates are halted when a “0” is written into the read
(TE) bit, B7, of Control register B (0Fh). As long as a “0”
remains in the Control register B (TE) bit, updating is
halted. After a halt is issued, the registers reflect the
RTC count (day, date, and time) that was current at the
moment the halt command was issued. Normal
updates to the external set of registers will resume
within 1 second after the (TE) bit is set to a “1”.
SETTING THE CLOCK
It is also recommended to halt updates to the external
set of double buffered RTC registers when writing to the
clock. The (TE) bit should be used as described above
before loading the RTC registers with the desired RTC
count (day, date, and time) in 24–hour BCD format. Set-
ting the (TE) bit to a “1” then transfers the values written
to the internal RTC registers and allows normal opera-
tion to resume.
CLOCK ACCURACY
A standard 32.768 kHz quartz crystal should be directly
connected to the DS1501 X1 and X2 oscillator pins. The
crystal selected for use should have a specified load
capacitance (CL) of either 6 pF or 12.5 pF depending on
crystal capacitance setting selected with the Crystal
Select (CS) bit. For more information on crystal selec-
tion and crystal layout considerations, please consult
Application Note 58, “Crystal Considerations with Dal-
las Real Time Clocks”. The DS1501 can also be driven
by an external 32.768 kHz oscillator. In this configura-
tion, the X1 pin is connected to the external oscillator
signal and the X2 pin is floated. Accuracy of DS1511 is
better than
±
1 min./month @ 25
°
C.
USING THE CLOCK ALARM
The alarm settings and control for the DS1501/DS1511
reside within registers 08h – 0Bh. Bit 7 of registers 08h
to 0Bh contains an alarm mask bit: AM1 thru AM4. The
TIE (Time of Day/Date alarm Interrupt Enable bit, B3 of
0Fh) and alarm mask bits AM1–AM4 must be set as
described below for the IRQ output to be activated for a
matched alarm condition.
The alarm can be programmed to activate on a specific
day of the month, day of the week, or repeat every day,
hour, minute, or second. It can also be programmed to
go off while the DS1501/DS1511 is in the battery backed
state of operation to serve as a system wake–up. Alarm
mask bits AM1–AM4 control the alarm mode. Table 3
shows the possible settings. Configurations not listed in
the table default to the once per second mode to notify
the user of an incorrect alarm setting. When the RTC