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参数资料
| 型号： | DS1501 |
| 厂商： | Maxim Integrated Products, Inc. |
| 英文描述： | Y2KC Watchdog Real Time Clock(Y2KC看门狗实时时钟) |
| 中文描述： | Y2K兼容、看门狗实时时钟 |
| 文件页数： | 9/22页 |
| 文件大小： | 178K |
| 代理商： | DS1501 |
DS1501/DS1511
071098 9/22
If V
CC
is applied within the time–out period, then the sys-
tem power on sequence will continue as shown in inter-
vals 2–5 in the timing diagram. During interval 2, PWR
will remain active and IRQ will be driven to its active low
level, indicating that either TDF or KSF was set in initiat-
ing the power on. In the diagram KS is assumed to be
pulled up to the V
BAUX
supply (logic high). Also at this
time, the PAB bit will be automatically cleared to “0” in
response to a successful power on. The PWR line will
remain active as long as the PAB remains cleared to “0”.
At the beginning of interval 3, the system processor has
begun code execution and clears the interrupt condition
of TDF and/or KSF by writing zeroes to both of these
control bits. As long as no other interrupt within the
DS1501 is pending, the IRQ line will be taken inactive
once these bits are reset, and execution of the applica-
tion software may proceed. During this time, both the
wakeup and kickstart functions may be used to gener-
ate status and interrupts. TDF will be set in response to
a day/date, hours, minutes, and seconds match condi-
tion. KSF will be set in response to a low going transition
on KS. If the associated interrupt enable bit is set (TDE
and/or KIE) then the IRQ line will be driven low in
response to enabled event. In addition, the other pos-
sible interrupt sources within the DS1501/DS1511 may
cause IRQ to be driven low. While system power is
applied, the on chip logic will always attempt to drive the
PWR pin active in response to the enabled kickstart or
wake up condition. This is true even if PWR was pre-
viously inactive as the result of power being applied by
some means other than wake up or kickstart.
The system may be powered down under software con-
trol by setting the PAB bit to a “1”. This causes the open–
drain PWR pin to be placed in a high impedance state,
as shown at the beginning of interval 4 in the timing dia-
gram. As V
CC
voltage decays, the IRQ output pin will be
placed in a high impedance state when V
CC
goes below
V
PF
. If the system is to be again powered on in response
to a wake up or kickstart, then both the TDF and KSF
flags should be cleared and TPE and/or KIE should be
enabled prior to setting the PAB bit.
During interval 5, the system is fully powered down. Bat-
tery backup of the clock calendar and nonvolatile RAM
is in effect and IRQ is tri–stated, and monitoring of wake
up and kickstart takes place. If PRS=“1”, PWR stays
active, otherwise if PRS=“0”, PWR is tri–stated.
SQUARE WAVE OUTPUT
The square wave output is enabled and disabled via the
‘E32K’ bit in the month register (B6 of 05h). If the square
wave is enabled (E32K = ‘1’) and the oscillator is
enabled, then a 32.768 kHz square wave will be output
on the SQW pin. If E32K= ‘1’ and the Battery Backup
32 kHz enable bit ‘BB32’ is enabled (B5 of 05h) and volt-
age is applied to V
BAUX
, then the 32 kHz square wave
signal will be output on the SQW pin in the absence of
V
CC
.
BATTERY MONITOR
Upon power–up, the DS1501/DS1511 checks the bat-
tery voltage of the back–up battery sources (V
BAT
and
V
BAUX
). The Battery Low Flag ‘VRT1’ and ‘VRT2’ bits of
control A register (B7 and B6 of 0Eh) will be set to a logic
1 at power–up if the battery voltage on V
BAT
and V
BAUX
are less than 2.5V (typical), otherwise VRT1 and VRT2
bits will be logic 0. VRT1 monitors V
BAT
with VRT2 moni-
toring V
BAUX
.
POWER–UP DEFAULT STATES
These bits are set upon power–up: EOSC=1, E32K=0,
TIE=0, KIE=0, WDE=0, and WDS=0.
256 X 8 EXTENDED RAM
The DS1501/DS1511 provides 256 x 8 of on–chip
SRAM which is controlled as nonvolatile data storage
sustained from a lithium battery. On power–up, the RAM
is taken out of write protect status by an internal signal.
Access to the SRAM is controlled by two on–chip latch
registers. One register is used to hold the SRAM
address, and the other is used to hold read/write data.
The SRAM address space is from 00h to FFh. The 8–bit
address of the RAM location to be accessed must be
loaded into the extended RAM address register located
at 10h. Data in the addressed location may be read by
performing a read operation from location 13h, or writ-
ten to by performing a write operation to location 13h.
When the Burst Mode Enable bit (B5 of control B
register 0Fh) is enabled (BME = ‘1’), the address pointer
in the extended RAM will automatically increment fol-
lowing each read/write operation. In this mode, the RAM
can be consecutively read or written without changing
the address in location 10h.
With burst mode disabled (BME = ‘0’), data in any
addressed location may be read or written repeatedly
without changing the address in location 10h.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1501_09 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Y2K-Compliant Watchdog Real-Time Clocks |
| DS1501-7R | 功能描述:EURO-CASSETTE 100W 15V RoHS:否 类别:电源 - 外部/内部（非板载） >> DC DC Converters 系列:* 标准包装:1 系列:Quint 类型:隔离 输入电压:24V 输出:24V 输出数:1 输出 - 1 @ 电流（最大）:24 VDC @ 50A 输出 - 2 @ 电流（最大）:- 输出 - 3 @ 电流（最大）:- 输出 - 4 @ 电流（最大）:- 功率（瓦特）:1200W 安装类型:底座安装 工作温度:0°C ~ 40°C 效率:- 封装/外壳:模块 尺寸/尺寸:4.33" L x 9.09" W x 6.14" H（110mm x 231mm x 156mm） 包装:散装 电源（瓦特）- 最大:1200W 批准:- 其它名称:277-69722866365-NDQUINT-BAT/24DC/12AH |
| DS1501-DS1511 | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Y2K-Compliant Watchdog Real-Time Clocks |
| DS1501W | 功能描述:IC RTC WDOG Y2KC 3.3V 28-DIP RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| DS1501W+ | 功能描述:实时时钟 Y2K-Compliant Watchdog RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
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