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参数资料
| 型号： | DS1610 |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Partitioned NV Controller(分割式非易失性控制器) |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDIP16 |
| 封装： | 0.300 INCH, DIP-16 |
| 文件页数： | 2/10页 |
| 文件大小： | 85K |
| 代理商： | DS1610 |
DS1610
022598 2/10
OPERATION – DISABLE PIN CONNECTED
TO V
CCO
The DS1610 performs five circuit functions required to
battery backup a RAM. First, a switch is provided to di-
rect power from the battery or the incoming power sup-
ply (V
CCI
) depending on which is greater. This switch
has a voltage drop of less than 0.2 volts. The second
function provided by the DS1610 is power fail detection.
The incoming supply (V
CCI
) is constantly monitored.
When the supply goes out of tolerance a precision com-
parator detects power failure and inhibits both the chip
enable output (CEO) and the write enable output
(WEO). A third function of write protection is accom-
plished by holding both the chip enable output CEO and
write enable output WEO to within 0.2 volts of V
CCO
when V
CCI
is out of tolerance. If CEI is low at the time
that power fail detection occurs the CEO signal is kept
low until CEI is brought high again. However, CEO is
forced high after 1.5
μ
sec regardless of the state of CEI.
Similarly, if WEI is low at the time that power fail detec-
tion occurs, the WEO is signal will remain low until WEI
is brought high or 1.5
μ
sec elapses. The delay of write
protection until the current memory cycle is complete
prevents corrupted data. Power fail detection occurs in
the range of 4.75 to 4.5 volts with the tolerance pin TOL
grounded. If the tolerance pin is connected to V
CCO
then power fail detection occurs in the range of 4.5 volts
to 4.25 volts. The PF0 signal is driven low and remains
low until V
CCI
returns to nominal conditions. During
nominal supply conditions CEO will follow CEI and
WEO will follow WEI. The fourth function which the
DS1610 performs is a battery status warning so that po-
tential data loss is avoided. Each time V
CCI
is applied to
the device battery status is checked with a precision
comparator. If during battery backup, no switch oc-
curred from one battery to the other, the voltage of the
battery supplying power when V
CCI
is applied is
checked. If this voltage is less than 2.0 volts the second
chip enable cycle after power is applied is inhibited. If
any switch from one battery to another did occur the
voltage of both batteries is checked. If either voltage is
less than 2.0 volts the second chip enable cycle will be
inhibited. Battery status can therefore be determined by
performing a read cycle after power up to any location in
memory, verifying that memory location’s contents. A
subsequent write cycle can then be executed to the
same memory location altering the data. If the next read
cycle fails to verify the written data then the data is in
danger of being corrupted. The fifth function of the
DS1610 provides for battery redundancy. When data
integrity is extremely important it is wise to use two bat-
teries to insure reliability. The DS1610 controller pro-
vides an internal isolation switch which allows the con-
nection of two batteries. When entering battery backup
operation, the battery with the highest voltage is se-
lected for use. If one battery should fail, the other would
then supply energy to the connected load. The switch to
a redundant battery is transparent to circuit operation
and to the user. In applications where battery redundan-
cy is not a major concern a single battery should be con-
nected to the BAT1 pin. The BAT2 battery pin must be
grounded. When batteries are first connected to one or
both of the V
BAT
pins V
CCO
will not show the battery po-
tential until V
CCI
is applied and removed for the first
time.
OPERATION – WRITE PROTECTION
PROGRAMMING MODE
When the disable pin is connected to V
CCI
or V
CCO
, the
DS1610 performs all of the functions described earlier
with the addition of a partition switch which selectively
write protects blocks of memory. The state of the DIS
pin is strobed and latched as V
CCI
crosses the power fail
trip point so that the DS1610 maintains its configuration
during power loss. If the strobed value of DIS is a high
the internal pulldown resistor on the DIS pin will be dis-
connected in the power fail state to eliminate the possi-
bility of battery discharge. The register controlling the
partition switch is selected by recognition of a specific
binary pattern which is sent on address lines A
W
-A
Z
.
These address lines are normally the four upper order
address lines being sent to RAM. The pattern is sent by
20 consecutive read cycles with the exact pattern as
shown in Table 1. Pattern matching must be accom-
plished using read cycles; any write cycles will reset the
pattern matching circuitry. If this pattern is matched per-
fectly, then the 21st through 24th read cycle will load the
partition switch. Since there are 16 possible write pro-
tected partitions, the size of each partition is determined
by the size of the memory. For example, a 128K X 8
memory would be divided into 16 partitions of 128K/16
or 8K X 8. Each partition is represented by one of the 16
bits contained in the 21st through 24th read cycle as de-
fined by A
W
through A
Z
and shown in Table 2. A logical 1
in a bit location sets that partition to write protect. A log-
ical 0 in a bit location disables write protection. For ex-
ample, if during the pattern match sequence bit 22 on
address pin A
X
was a 1, this would cause the partition
register location for partition 5 to be set to a 1. This in
turn would cause the DS1610 to inhibit WEO from going
low as WEI goes low whenever A
Z
A
Y
A
X
A
W
=0101. Note
that while setting the partition register, data which is be-
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相关代理商/技术参数 |
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