参数资料
型号: DS17285S-3+T&R
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: XO, clock
英文描述: 3V/5V Real-Time Clock
中文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO24
封装: SO-24
文件页数: 15/38页
文件大小: 411K
代理商: DS17285S-3+T&R
DS17285/DS17287
22 of 38
EXTENDED CONTROL REGISTER 4B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ABE
E32k
CS
RCE
PRS
RIE
WIE
KSE
ABE – Auxiliary Battery Enable. This bit when written to a logic 1 enables the VBAUX pin for extended
functions.
E32k – Enable 32.768kHz Output. This bit when written to a logic 1 enables the 32.768kHz oscillator
frequency to be output on the SQW pin. E32k is set to a 1 when VCC is powered up.
CS – Crystal Select. When CS is set to a 0, the oscillator is configured for operation with a crystal that
has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal. CS is
disabled in the DS17287 module and should be set to CS = 0.
RCE – RAM Clear Enable. When set to a 1, this bit enables a low level on RCLR to clear all 114 bytes
of user RAM. When RCE = 0, RCLR and the RAM clear function are disabled.
PRS – PAB Reset Select. When set to a 0, the PWR pin is set high-z when the DS17285 goes into power
fail. When set to a 1, the PWR pin remains active upon entering power fail.
RIE – RAM Clear Interrupt Enable. When RIE is set to a 1, the IRQ pin is driven low when a RAM
clear function is completed.
WIE – Wake-up Alarm Interrupt Enable. When VCC voltage is absent and WIE is set to a 1, the PWR
pin is driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When VCC is
then applied, the IRQ pin is also driven low. If WIE is set while system power is applied, both IRQ and
PWR
are driven low in response to WF being set to 1. When WIE is cleared to a 0, the WF bit has no
affect on the PWR or IRQ pins.
KSE – Kickstart Interrupt Enable. When VCC voltage is absent and KSE is set to a 1, the PWR pin is
driven active low when a kickstart condition occurs ( KS pulsed low), causing the KF bit to be set to 1.
When VCC is then applied, the IRQ pin is also driven low. If KSE is set to 1 while system power is
applied, both IRQ and PWR are driven low in response to KF being set to 1. When KSE is cleared to a 0,
the KF bit has no affect on the PWR or IRQ pins.
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