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| 型号： | DS1846E-010+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/18页 |
| 文件大小： | 0K |
| 描述： | IC NV TRI-POT MEM MON 20TSSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 74 |
| 接片： | 100，256 |
| 电阻（欧姆）： | 10k，100k |
| 电路数： | 3 |
| 温度系数： | 标准值 750 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | 3 线串行（设备位址） |
| 电源电压： | 4.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1430 (CN2011-ZH PDF) |
DS1846
7 of 18
2-WIRE SERIAL PORT OPERATION
The 2-wire serial port interface supports a bidirectional data transmission protocol with device
addressing. A device that sends data on the bus is defined as a transmitter, and a device receiving data as
a receiver. The device that controls the message is called a “master.” The devices that are controlled by
the master are “slaves.” The bus must be controlled by a master device that generates the serial clock
(SCL), controls the bus access, and generates the start and stop conditions. The DS1846 operates as a
slave on the 2-wire bus. Connections to the bus are made through the open-drain I/O lines, SDA and SCL.
The following I/O terminals control the 2-wire serial port: SDA, SCL, and A0. Timing diagrams for the
2-wire serial port can be found in Figures 2 and 3. Timing information for the 2-wire serial port is
provided in the AC ELECTRICAL CHARACTERISTICS table for 2-wire serial communications.
The following bus protocol has been defined:
§ Data transfer may be initiated only when the bus is not busy.
§ During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high are interpreted as control signals.
Accordingly, the following bus conditions have been defined:
Bus Not Busy: Both data and clock lines remain high.
Start Data Transfer: A change in the state of the data line from high to low while the clock is high
defines a start condition.
Stop Data Transfer: A change in the state of the data line from low to high while the clock line is high
defines the stop condition.
Data Valid: The state of the data line represents valid data when, after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line can be changed during
the low period of the clock signal. There is one clock pulse per bit of data. Figures 2 and 3 detail how
data transfer is accomplished on the 2-wire bus. Depending upon the state of the R/W bit, two types of
data transfer are possible.
Each data transfer is initiated with a start condition and terminated with a stop condition. The number of
data bytes transferred between start and stop conditions is not limited and is determined by the master
device. The information is transferred byte-wise and each receiver acknowledges with a ninth bit.
Within the bus specifications, a regular mode (100kHz clock rate) and a fast mode (400kHz clock rate)
are defined. The DS1846 works in both modes.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1846E-010/R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:NV Tri-Potentiometer, Memory, and MicroMonitor |
| DS1846E-010/T | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:NV Tri-Potentiometer, Memory, and MicroMonitor |
| DS1846E-010/T&R | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:NV Tri-Potentiometer, Memory, and MicroMonitor |
| DS1846E-010+ | 功能描述:数字电位计 IC NV Tri-Potentiometer Memory/MicroMonitor RoHS:否 制造商:Maxim Integrated 电阻:200 Ohms 温度系数:35 PPM / C 容差:25 % POT 数量:Dual 每 POT 分接头:256 弧刷存储器:Volatile 缓冲刷: 数字接口:Serial (3-Wire, SPI) 描述/功能:Dual Volatile Low Voltage Linear Taper Digital Potentiometer 工作电源电压:1.7 V to 5.5 V 电源电流:27 uA 最大工作温度:+ 125 C 安装风格:SMD/SMT 封装 / 箱体:TQFN-16 封装:Reel |
| DS1846E-010+T&R | 制造商:Maxim Integrated Products 功能描述:DGTL POTENTIOMETER 100/256POS 10KOHM/100KOHM TRIPLE 20TSSOP - Tape and Reel 制造商:Maxim Integrated Products 功能描述:IC NV TRI-POT MEM MON 20TSSOP 制造商:Maxim Integrated Products 功能描述:Digital Potentiometer ICs NV Tri-Potentiometer Memory/MicroMonitor |
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