参数资料
型号: DS1861B+
厂商: Maxim Integrated
文件页数: 12/25页
文件大小: 0K
描述: IC LASR CTRLR 1CHAN 5.5V 16CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 810
类型: 激光二极管控制器(光纤)
通道数: 1
电源电压: 2.85 V ~ 5.5 V
电流 - 电源: 5mA
工作温度: -40°C ~ 95°C
封装/外壳: 16-LBGA,CSPBGA
供应商设备封装: 16-CSBGA(4x4)
包装: 托盘
安装类型: 表面贴装
Full Laser Control with Fault Management
Functional Diagram
V CC
USER EEPROM
V CC
(8 BYTES)
DISTURBANCE
CURRENT
I DIST
SDA
SCL
I 2 C-COMPATIBLE
INTERFACE
WITH SETTINGS
PASSWORD
AUTOMATIC
POWER CONTROL
NONVOLATILE
I B
I BMD
Σ
BIASSET
A 2
PROTECTION
MODSET
A 1
A 0
AUTOMATIC
EXTINCTION
RATIO CONTROL
NONVOLATILE
I BMD
V REF
TX-D
R BMD
TX-F
QUICK TRIP
I B
FAULT MONITOR
NONVOLATILE
I BMD
V CC
I SET
CURRENT
SENSE
BMD
GND
DS1861
Detailed Description
Automatic Power Control
The DS1861 APC is accomplished by adjusting the
bias current (I BIAS ) until the feedback current (I BMD )
from a photodiode matches the value determined by
the APC register. The relationship between the APC
register and I BMD is given by:
I SET = 1.525μA Gain (APC<4:0> + 32)
where APC<4:0> is the numerical value determined by
the five least significant bits of the APC register, and
the gain value is determined by the upper three bits of
the APC register, as shown in the truth table below. See
Figure 7 for a graph of the BMD current-set point vs.
the APC register value.
CURRENT
SINK/SOURCE
The BMD pin appears to the photodiode as a voltage
source (V REF ) with an output resistance equal to R BMD
in parallel with a current source (I SET ) equal to the I BMD
setpoint. When the control loop is at its steady state
value, the voltage at the BMD pin (V BMD ) is equal to
V REF , and the BMD current will all be sourced by I SET .
When an imbalance causes the feedback current to differ
from the set current, the difference in the currents causes
the DS1861 to adjust the BIASSET and the MODSET cur-
rents to new settings so the input current matches the
set current. During transient periods, the difference in
the I SET and I BMD currents causes a small current to
pass through R BMD . This causes a slight increase or
decrease in the V BMD voltage. The current source can
sink and source current, which must be configured using
the DPOL bit in the control byte for proper operation.
APC<7:5>
000
001
010
011
1xx
GAIN
1
2
4
8
16
This allows the photodiode to be referenced to either
V CC or GND. See the Memory Map and Detailed
Register Descriptions sections for more detail.
12
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