参数资料
型号: DS1861E+
厂商: Maxim Integrated
文件页数: 6/25页
文件大小: 0K
描述: IC LASR CTRLR 1CHAN 5.5V 14TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
类型: 激光二极管控制器(光纤)
通道数: 1
电源电压: 2.85 V ~ 5.5 V
电流 - 电源: 5mA
工作温度: -40°C ~ 95°C
封装/外壳: 14-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 14-TSSOP
包装: 管件
安装类型: 表面贴装
Full Laser Control with Fault Management
NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +2.85V to 5.5V, T A = 0°C to +70°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Writes
+70°C (Note 15)
50,000
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
All voltages are referenced to ground. Currents into the IC are positive, out of the IC negative.
The threshold current (I TH ) to light producing current (I APC ) ratio should remain below 7:1. This limits overshoot to under
10% and ensures the data sheet accuracies are met.
Max I CC is dependent on SCL clock rates.
Calibration accuracy refers to the accuracy achieved at the end of calibration.
This specification refers to the error contribution due to this chip, and does not include the error due to the drift of the mon-
itor-diode responsivity with temperature.
The N Temperature Drift specification includes error caused by changes in modulation current due to system temperature
variation. After the part is calibrated at +25°C, this spec allows for modulation current changes of up to +65% with increas-
ing temperature and -25% with decreasing temperature. Larger modulation current variations would have increased drift,
but this range accommodates a reasonable change (up to 2x across temperature) in laser diode slope efficiency.
Calibration is assumed to take place at +25°C for the purposes of this spec. This does not imply that the system must be
calibrated at +25°C.
Within the APC calibration accuracy.
Values in the table are multiplied times the I BMD set point (set by APC register) to determine the threshold limits.
I 2 C interface timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I 2 C stan-
dard-mode timing.
C B —total capacitance of one bus line in pF.
EEPROM write begins after a stop condition occurs.
If the supply ramps up at slew rates within the specification, the device will be functional after V CC exceeds V POA and the
power-up time (t POAR ) elapses.
On power-up and when TX-D is deasserted, IBIASSET ramps up from zero current to its final value with ≤ 10% APC over-
shoot during the transient.
Modulation is applied at the level it was at before disable. If the time from disable is so long that the laser has cooled
down, then meeting ER accuracy is contingent upon completion of the first ER update. The MODLOAD enable bit and
MODLOAD register can be used to load a predetermined I MODSET value if desired. See the Detailed Register Descriptions
section for more information.
This parameter is guaranteed by design.
6
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