参数资料
型号: DS1863E+T&R
厂商: Maxim Integrated
文件页数: 9/62页
文件大小: 0K
描述: IC LASR CTRLR 1CHAN 5.5V 16TSSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1,000
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 5.5 V
电流 - 电源: 5mA
电流 - 偏置: 1.2mA
工作温度: -40°C ~ 95°C
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 带卷 (TR)
安装类型: 表面贴装
Burst-Mode PON Controller
With Integrated Monitoring
Modulation Control
The MOD voltage is controlled using an internal tem-
perature indexed Lookup Table.
The MOD output is an 8-bit scaleable voltage output that
interfaces with the MAX3643 ’ s VMSET input. An external
resistor to ground from the MAX3643 ’ s MODSET pin sets
the maximum current the voltage at VMSET input can
produce for a given output range. This resistor value
should be chosen to produce the maximum modulation
current the laser type requires over temperature. The
modulation LUT can be programmed in 2 ° C increments
over the -40 ° C to +102 ° C range to provide temperature
compensation for the laser ’ s modulation. The modulation
DAC ’ s scaling can be used (with APC scaling) to imple-
ment GPON power leveling with a single LUT that works
for all three power levels.
Ranging of the MOD DAC is possible by programming
a single byte in Table 02h.
BIAS and MOD Output During
Initial Power-Up
On power-up the modulation and bias outputs will
remain off until V CC is above V POA , a temperature con-
version has been completed, and if the V CC LO ADC
alarm is enabled, then a V CC conversion above the
customer defined V CC low alarm level has cleared the
V CC low alarm. Once all of these conditions are satis-
POWER-UP TIMING
V POA
fied, the MOD output will be enabled with the value
determined by the temperature conversion and the
modulation LUT.
When the MOD output is enabled and BEN is high, the
I BIAS DAC output will be turned on to a value equal to
I STEP (see above). The start-up algorithm checks if this
bias current causes a feedback voltage above the APC
set-point, and if it does not it continues increasing the
I BIAS by I STEP until the APC set-point is exceeded.
When the APC set point is exceeded, the device will
begin a binary search to quickly reach the bias current
corresponding to the proper power level. After the bina-
ry search is completed the APC integrator is enabled,
and single LSB steps are taken to tightly control the
average power.
All quick-trip and ADC alarm flags are masked until the
binary search is completed. However, the BIAS MAX
alarm is monitored during this time to prevent the bias
output from exceeding MAX IBIAS. During the bias cur-
rent initialization, the bias current is not allowed to
exceed MAX IBIAS. If this occurs during the I STEP
sequence then the binary search routine is enabled. If
MAX IBIAS is exceeded during the binary search, then
the next smaller step is activated. I STEP or binary incre-
ments that would cause I BIAS to exceed MAX IBIAS are
not taken. Many of the alarm sources are likely to trip
V CC
t ON
MOD
VOLTAGE
t SEARCH
4x I STEP
BIAS
CURRENT
3x I STEP
BINARY SEARCH
APC
INTEGRATOR
ON
2x I STEP
I STEP
BIAS
SAMPLE
1
2
3
4
5
6
7
8
9
10
11
12
13
Figure 1. DS1863 Power-Up.
_____________________________________________________________________
9
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