参数资料
型号: DS1874T+T&R
厂商: Maxim Integrated
文件页数: 61/88页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 带卷 (TR)
安装类型: 表面贴装
其它名称: 90-1874T+TRL
SFP+ Controller with Digital LDD Interface
Table 02h, Register 8Bh: CNFGC
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
00h
PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
8Bh
RESERVED
RESERVED
TXDM34
TXDFG
TXDFLT
TXDIO
RSSI_FC
RSSI_FF
BIT 7
BITS 7:6
BIT 5
BIT 4
BIT 3
BIT 2
BITS 1:0
BIT 0
RESERVED
TXDM34: Enables TXD to reset alarms and warnings associated to MON3 and MON4 during a TXD
event.
0 = TXD event has no effect on the MON3 and MON4 alarms, warnings, and quick trips.
1 = MON3 and MON4 alarms, warnings, and quick trips are reset during a TXD event.
TXDFG: See Figure 12.
0 = FETG, an internal signal, has no effect on TXDOUT.
1 = FETG is enabled and ORed with other possible signals to create TXDOUT.
TXDFLT: See Figure 12.
0 = TXF pin has no effect on TXDOUT.
1 = TXF pin is enabled and ORed with other possible signals to create TXDOUT.
TXDIO: See Figure 12.
0 = (Default) TXD input signal is enabled and ORed with other possible signals to create TXDOUT.
1 = TXD input signal has no effect on TXDOUT.
RSSI_FC and RSSI_FF: RSSI Force Coarse and RSSI Force Fine. Control bits for RSSI mode of
operation on the MON3 conversion.
00b = Normal RSSI mode of operation (default).
01b = The fine settings of scale and offset are used for MON3 conversions.
10b = The coarse settings of scale and offset are used for MON3 conversions.
11b = Normal RSSI mode of operation.
Table 02h, Register 8Ch: DEVICE ADDRESS
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE
00h
PW2 or (PW1 and RWTBL246) or (PW1 and RTBL246)
PW2 or (PW1 and RWTBL246)
Nonvolatile (SEE)
8Ch
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
BIT 7
BIT 0
This value becomes the I 2 C slave address for the main memory when the ASEL (Table 02h, Register 89h) bit is
set. If A0h is programmed to this register, the auxiliary memory is disabled.
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