参数资料
型号: DS1884T+
厂商: Maxim Integrated Products
文件页数: 16/92页
文件大小: 0K
描述: IC SFP PON ONU CTRLR 24TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
产品变化通告: DS1884 Series Discontinuation 03/Aug/2012
标准包装: 28
系列: *
DS1884
SFP and PON ONU Controller
with Digital LDD Interface
23
Maxim Integrated
Low-Voltage Operation
The DS1884 contains two power-on reset (POR) levels.
The lower level is a digital POR (POD) and the higher
level is an analog POR (POA). At startup, before the sup-
ply voltage rises above POA, the outputs are disabled,
all SRAM locations are set to their defaults, shadowed
EEPROM locations are zero, and all analog circuitry is
disabled. When VCC reaches POA, the SEE is recalled,
and the analog circuitry is enabled. While VCC remains
above POA, the device is in its normal operating state,
and it responds based on its nonvolatile configuration. If
during operation VCC falls below POA, but is still above
POD, the SRAM retains the SEE settings from the first
SEE recall, but the device analog is shut down and the
outputs are disabled. If the supply voltage recovers back
above POA, the device immediately resumes normal
operation. If the supply voltage falls below POD, the
device SRAM is placed in its default state and another
SEE recall is required to reload the nonvolatile settings.
The EEPROM recall occurs the next time VCC next
exceeds POA. Figure 7 shows the sequence of events
as the voltage varies.
Any time VCC is above POD, the I2C interface can be
used to determine if VCC is below the POA level. This is
accomplished by checking the RDYB bit in the STATUS
when VCC is below POA; when VCC rises above POA,
RDYB is timed (within 500Fs) to go to 0, at which point
the part is fully functional.
For all device addresses sourced from EEPROM (A2h
Table 02h, Register 8Ch), the default DEVICE ADDRESS
is A2h until VCC exceeds POA, allowing the device
address to be recalled from the EEPROM.
Power-On Analog (POA)
POA holds the DS1884 in reset until VCC is at a suitable
level (VCC > POA) for the device to accurately measure
with its ADC and compare analog signals with its quick-
trip monitors. Because VCC cannot be measured by the
ADC when VCC is less than POA, POA also asserts the
VCC LO alarm, which is cleared by a VCC ADC conver-
sion greater than the customer-programmable VCC low
ADC limit. This allows a programmable limit to ensure
that the head room requirements of the transceiver are
satisfied during a slow power-up. The TXFOUT output
does not latch until there is a conversion above the VCC
low limit. The POA alarm is nonmaskable. See the Low-
Voltage Operation section for more information.
Table 3. RSSI Hysteresis Threshold Values
Table 4. RSSI Configuration Registers
*This is the minimum reported coarse mode conversion.
# OF RIGHT-
SHIFTS
FINE MODE
MAX (HEX)
COARSE MODE
MIN* (HEX)
0
FFF8h
F000h
1
7FFCh
7800h
2
3FFEh
3C00h
3
1FFFh
1E00h
4
0FFFh
0F00h
5
07FFh
0780h
6
03FFh
03C0h
7
01FFh
01E0h
REGISTER
FINE MODE
COARSE MODE
Gain Register (RSSI FINE/COARSE
SCALE)
98h–99h, A2h Table 02h
9Ch–9Dh, A2h Table 02h
Offset Register (RSSI FINE/COARSE
OFFEST)
A8h–A9h, A2h Table 02h
ACh–ADh, A2h Table 02h
RIGHT-SHIFT1 Register
8Eh, A2h Table 02h
N/A
RSSIC and RSSIF Bits (RIGHT-SHIFT0)
8Fh, A2h Table 02h
RSSIR Bit (UPDATE)
6Fh, A2h Lower Memory
RSSI Measurement (RSSI VALUE)
68h–69h, A2h Lower Memory
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