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| 型号： | DS21348TN+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 46/76页 |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 3.3V 44-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 1/1 |
| 规程： | T1/E1/J1 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 1429 (CN2011-ZH PDF) |
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DS21348/DS21Q348
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7.2 Transmitter
The DS21348 uses a set of laser-trimmed delay lines along with a precision Digital-to-Analog Converter
(DAC) to create the waveforms that are transmitted onto the E1 or T1 line. The waveforms created by the
DS21348 meet the latest ETSI, ITU, ANSI, and AT&T specifications. The user will select which
waveform is to be generated by setting the ETS bit (CCR1.7) for E1 or T1 operation, then programming
the L2/L1/L0 bits in Common Control Register 4 for the appropriate application. See Table 7-1 and
Table 7-2 for the proper L2/L1/L0 settings.
A 2.048MHz or 1.544MHz TTL clock is required at TCLK for transmitting data at TPOS and TNEG.
ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs
require an accuracy of ±32ppm for T1 interfaces. The clock can be sourced internally by RCLK or
JACLK. See CCR1.2, CCR1.1, CCR1.0, and Figure 1-3 for details. Due to the nature of the design of the
transmitter in the DS21348, very little jitter (less than 0.005UIP-P broadband from 10Hz to 100kHz) is
added to the jitter present on TCLK. Also, the waveforms created are independent of the duty cycle of
TCLK. The transmitter in the DS21348 couples to the E1 or T1 transmit twisted pair (or coaxial cable in
some E1 applications) via a 1:2 step-up transformer. In order for the device to create the proper
waveforms, the transformer used must meet the specifications listed in Table 7-3.
The DS21348 has automatic short-circuit limiter which limits the source current to 50mA (RMS) into a
1 load. This feature can be disabled by setting the SCLD bit (CCR2.5) = 1. When the current limiter is
activated, TCLE (SR.2) will be set even if short circuit limiter is disabled. The TPD bit (CCR4.0) will
power-down the transmit line driver and tri-state the TTIP and TRING pins. The DS21348 can also detect
when the TTIP or TRING outputs are open circuited. When an open circuit is detected, TOCD (SR.1)
will be set.
7.3 Jitter Attenuator
The DS21348 contains an on-board jitter attenuator that can be set to a depth of either 32 or 128 bits via
the JABDS bit (CCR4.2). In hardware mode the depth is 128 bits and cannot be changed. The 128-bit
mode is used in applications where large excursions of wander are expected. The 32-bit mode is used in
delay sensitive applications. The characteristics of the attenuation are shown in Figure 7-7Figure 7-7. The
jitter attenuator can be placed in either the receive path or the transmit path by appropriately setting or
clearing the JAS bit (CCR4.3). Also, the jitter attenuator can be disabled (in effect, removed) by setting
the DJA bit (CCR4.1). For the jitter attenuator to operate properly, a 2.048MHz or 1.544MHz clock must
be applied at MCLK. ITU specification G.703 requires an accuracy of ±50ppm for both T1 and E1.
TR62411 and ANSI specs require an accuracy of ±32ppm for T1 interfaces. There is an on-board PLL for
the jitter attenuator, which will convert the 2.048MHz clock to a 1.544 MHz rate for T1 applications.
Setting JAMUX (CCR1.3) to a logic 0 bypasses this PLL. On-board circuitry adjusts either the recovered
clock from the clock/data recovery block or the clock applied at the TCLK pin to create a smooth jitter-
free clock, which is used to clock data out of the jitter attenuator FIFO. It is acceptable to provide a
gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If the incoming
jitter exceeds either 120UIP-P (buffer depth is 128 bits) or 28UIP-P (buffer depth is 32 bits), then the
DS21348 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either 15 or 17
instead of the normal 16 to keep the buffer from overflowing. When the device divides by either 15 or 17,
it also sets the Jitter Attenuator Limit Trip (JALT) bit in the Receive Information Register 1 (RIR1).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21348TN+ | 功能描述:网络控制器与处理器 IC 3.3V E1/T1/J1 Line Interface RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21348TNB | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21348T-W | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21349 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:3.3V T1/J1 Line Interface Unit |
| DS21349DK | 功能描述:网络开发工具 DS21349 Design Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
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