参数资料
型号: DS21352LB
厂商: Maxim Integrated Products
文件页数: 109/137页
文件大小: 0K
描述: IC TXRX 1-CHIP T1 3.3V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
产品变化通告: Product Discontinuation 20/Feb/2012
标准包装: 90
功能: 单芯片收发器
接口: HDLC,T1
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
DS21352/DS21552
73 of 137
RHIR: RECEIVE HDLC INFORMATION REGISTER (Address=03 Hex)
(MSB)
(LSB)
RABT
RCRCE
ROVR
RVM
REMPTY
POK
CBYTE
OBYTE
SYMBOL
POSITION
NAME AND DESCRIPTION
RABT
RHIR.7
Abort Sequence Detected. Set whenever the HDLC controller sees 7 or more ones in a
row.
RCRCE
RHIR.6
CRC Error. Set when the CRC checksum is in error.
ROVR
RHIR.5
Overrun. Set when the HDLC controller has attempted to write a byte into an already full
receive FIFO.
RVM
RHIR.4
Valid Message. Set when the HDLC controller has detected and checked a complete
HDLC packet.
REMPTY
RHIR.3
Empty. A real–time bit that is set high when the receive FIFO is empty.
POK
RHIR.2
Packet OK. Set when the byte available for reading in the receive FIFO is the last byte of
a valid message (and hence no abort was seen, no overrun occurred, and the CRC was
correct).
CBYTE
RHIR.1
Closing Byte. Set when the byte available for reading in the receive FIFO is the last byte
of a message (whether the message was valid or not).
OBYTE
RHIR.0
Opening Byte. Set when the byte available for reading in the receive FIFO is the first byte
of a message.
NOTE:
The RABT, RCRCE, ROVR, and RVM bits are latched and will be cleared when read.
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