参数资料
型号: DS21458DK
厂商: Maxim Integrated Products
文件页数: 3/32页
文件大小: 0K
描述: KIT DESIGN FOR G511DS21458
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS21458DK Gerber Files
标准包装: 1
主要目的: 电信,线路接口单元(LIU)
已用 IC / 零件: DS21458
已供物品: 板,子卡,CD
DS21458DK, Quad T1/E1/J1 Transceiver Design Kit Daughter Card
BOARD FLOORPLAN
RLOS 4-1 LEDs
Dallas
Semiconductor
DS21458
FPGA
IMPEDANCE
MATCHING/
LINE
PROTECTION
FPGA
STATUS
LED
LINE
PROTECTION
PORT 4
LINE
PROTECTION
PORT 3
LINE
PROTECTION
PORT 2
LINE
BNC
PORT
4
BNC
PORT
3
BNC
PORT
2
BNC
JTAG
FPGA
CONFIG
PROM
2.5V FPGA
SUPPLY
PROTECTION
PORT 1
PORT
1
BASIC CONFIGURATION
This design kit relies upon several supporting files, which are available for downloading on our website at
www.maxim-ic.com/telecom . See the DS21458DK QuickView data sheet for these files.
Hardware Configuration
Using the DK101 Processor Board:
·
·
·
·
Connect the daughter card to the DK101 processor board.
Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector is
unused. Additionally, the TIM 5V supply headers are unused.)
All processor board DIP switch settings should be in the ON position with exception of the flash programming
switch, which should be OFF.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs ?
ChipView ? ChipView.
Using the DK2000 Processor Board:
·
·
·
Connect the daughter card to the DK2000 processor board.
Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply may be connected
to connector J2.
From the Programs menu, launch the host application named ChipView.EXE. Run the ChipView application. If
the default installation options were used, click the Start button on the Windows toolbar and select Programs ?
ChipView ? ChipView.
General
·
·
Upon power-up, the RLOS LEDs (green) will not be lit, the INT LED (red) will not be lit, but the FPGA Status
LED (green) will be lit.
When operating in E1 mode, slide SW1–SW4 to E1 Mode (grounding the BNC shell). When operating in T1
mode, slide SW1–SW4 to T1 Mode.
Miscellaneous
·
·
·
Clock frequencies and certain pin bias levels are provided by a register-mapped FPGA that is on the DS21458
daughter card.
The definition file for this FPGA is named DS21458DC_FPGA.def. See Table 2 for the FPGA Register Map
definitions. A drop-down menu on the top of the screen allows for switching between definition files.
All files referenced above are available for download as described in the Basic Configuration section.
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