参数资料
型号: DS21458DK
厂商: Maxim Integrated Products
文件页数: 9/32页
文件大小: 0K
描述: KIT DESIGN FOR G511DS21458
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
设计资源: DS21458DK Gerber Files
标准包装: 1
主要目的: 电信,线路接口单元(LIU)
已用 IC / 零件: DS21458
已供物品: 板,子卡,CD
DS21458DK, Quad T1/E1/J1 Transceiver Design Kit Daughter Card
Register Name: SYSCLKR
Register Description: DS21458 RSYSCLK Pin Setting
Register Offset: 0x0014
Bit #
Name
Default
7
T4S1
0
6
T4S0
0
5
T3S1
0
4
T3S0
0
3
T2S1
0
2
T2S0
0
1
T1S1
0
0
T1S0
0
Bit 0 to 1: DS21458 Port 1 RSYSCLK Source (T1S0, T1S1)
The source for RSYSCLK 1 is Defined as shown in Table 5.
Bit 2 to 3: DS21458 Port 2 RSYSCLK Source (T2S0, T2S1)
The source for RSYSCLK 2 is Defined as shown in Table 5.
Bit 4 to 5: DS21458 Port 3 RSYSCLK Source (T3S0, T3S1)
The source for RSYSCLK 3 is Defined as shown in Table 5.
Bit 6 to 7: DS21458 Port 4 RSYSCLK Source (T4S0, T4S1)
The source for RSYSCLK 4 is Defined as shown in Table 5.
Table 5. RSYSCLKx Source Definition
TxS1, TxS0
00
01
10
11
RSYSCLK X CONNECTION
Drive RSYSCLK X with the 1.544MHz clock
Drive RSYSCLK X with the 2.048MHz clock
Drive RSYSCLK X with 8.192MHz clock
Drive RSYSCLK X with DS21458 Port X BPCLK
Register Name: SYNC1
Register Description: DS21458 TSYNC Pin Source
Register Offset: 0x0015
Bit #
Name
Default
7
6
5
4
3
T4SRC
0
2
T3SRC
0
1
T2SRC
0
0
T1SRC
0
Bit 0: DS21458 Port 1 TSYNC Source (T1SRC)
0 = TSYNC 1 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 1 with RSYNC 1
Bit 1: DS21458 Port 2 TSYNC Source (T2SRC)
0 = TSYNC 2 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 2 with RSYNC 2
Bit 2: DS21458 Port 3 TSYNC Source (T3SRC)
0 = TSYNC 3 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 3 with RSYNC 3
Bit 3: DS21458 Port 4 TSYNC Source (T4SRC)
0 = TSYNC 4 is an output, tri-state corresponding FPGA driver pin (weak pulldown)
1 = Drive TSYNC 4 with RSYNC 4
Note: When driving TSYNCx with RSYNCx the corresponding DS21458 port should be configured such that
TSYNCx is an input (IOCR1.1 = 0) and RSYNCx is an output (IOCR1.4 = 0).
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