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参数资料
| 型号： | DS2152L |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP100 |
| 封装： | LQFP-100 |
| 文件页数： | 4/14页 |
| 文件大小： | 1398K |
| 代理商： | DS2152L |
12
Maxim Integrated
Adjustable Overvoltage and Overcurrent
Protectors with High Accuracy
MAX14571/MAX14572/MAX14573
Figure 5a. Human Body ESD Test Model
Figure 5b. Human Body Current Waveform
OUT Bypass Capacitor
For stable operation over the full temperature range
and over the entire programmable current-limit range,
connect a 1FF ceramic capacitor from OUT to ground.
Excessive output capacitance can cause a false over-
current condition due to decreased dV/dt across the
capacitor. Calculate the maximum capacitive load
(CMAX) value that can be connected to OUT by using
the following formula:
= LIM
BLANK(MIN)
MAX
IN
I
(mA) x t
(ms)
C
(F)
V (V)
For example, for VIN = 24V, tBLANK = 15ms, and ILIM =
4.2A, CMAX equals 2625FF.
Output Freewheeling Diode for
Inductive Hard Short to Ground
In applications that require protection form a sudden
short to ground with an inductive load or long cable, a
Schottky diode between the OUT terminal and ground
is recommended. This is to prevent a negative spike on
OUT due to the inductive kickback during a short-circuit
event.
Layout and Thermal Dissipation
To optimize the switch response time to output short-
circuit conditions, it is very important to keep all traces
as short as possible to reduce the effect of undesirable
parasitic inductance. Place input and output capaci-
tors as close as possible to the device (no more than
5mm). IN and OUT must be connected with wide short
traces to the power bus. During normal operation, the
power dissipation is small and the package temperature
change is minimal. If the output is continuously shorted
to ground at the maximum supply voltage, the switches
with the autoretry option do not cause thermal-shutdown
detection to trip:
IN(MAX)
OUT(MAX)
BLANK
(MAX)
RETRY
BLANK
V
I
t
P
t
××
=
+
Attention must be given to the MAX14573 continuous
current-limit version when the power dissipation dur-
ing a fault condition can cause the device to reach
the thermal-shutdown threshold. Thermal vias from the
exposed pad to ground plane are highly recommended
to increase the system thermal capacitance while reduc-
ing the thermal resistance to the ambient.
ESD Test Conditions
The devices are specified for Q15kV (HBM) typical ESD
resistance on IN when IN is bypassed to ground with a
1FF low-ESR ceramic capacitor. No capacitor is required
for Q2kV (HBM) typical ESD on IN. All the pins have a
Q
2kV (HBM) typical ESD protection.
HBM ESD Protection
Figure 5a shows the Human Body Model, and Figure
5b shows the current waveform it generates when dis-
charged into a low impedance. This model consists of a
100pF capacitor charged to the ESD voltage of interest,
which is then discharged into the device through a 1.5kI
resistor.
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
Cs
100pF
RC
1MI
RD
1.5kI
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
IP 100%
90%
36.8%
tRL
TIME
tDL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
IR
10%
0
AMPERES
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