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参数资料
型号： DS21554LBN+
厂商： Maxim Integrated Products
文件页数： 117/124页
文件大小： 0K
描述： IC TXRX E1 5V 100-LQFP
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 90
功能： 单芯片收发器
接口： E1，HDLC，J1，T1
电路数： 1
电源电压： 4.75 V ~ 5.25 V
电流 - 电源： 75mA
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LQFP
供应商设备封装： 100-LQFP（14x14）
包装： 托盘
包括： 远程和 AIS 警报检测器 / 发生器
DS21354/DS21554 3.3V/5V E1 Single-Chip Transceivers
92 of 124
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK. See Figure 16-2.
Test-Logic-Reset
Upon power up, the TAP Controller will be in the Test-Logic-Reset state. The Instruction register will
contain the IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and
test registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the Capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the Select-IR-Scan state.
Capture-DR
Data may be parallel-loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the Shift-
DR state if JTMS is LOW or it will go to the Exit1-DR state if JTMS is HIGH.
Shift-DR
The test data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage towards its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the Update-DR state, which
terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put
the controller in the Pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A
rising edge on JTCLK with JTMS HIGH will put the controller in the Exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the Update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the Shift-
DR state.
Update-DR
A falling edge on JTCLK while in the Update-DR state will latch the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register.
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相关代理商/技术参数
参数描述
DS21554LBN+ 功能描述:网络控制器与处理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21554LN 功能描述:网络控制器与处理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS21554LN+ 功能描述:网络控制器与处理器 IC 3.3/5V E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS2155DK 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
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