参数资料
型号: DS2180AQN/T&R
厂商: Maxim Integrated Products
文件页数: 20/35页
文件大小: 0K
描述: IC TRANSCEIVER T1 IND 44-PLCC
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 500
功能: 收发器
接口: T1
电路数: 1
电源电压: 4.5 V ~ 5.5 V
电流 - 电源: 3mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-LCC(J 形引线)
供应商设备封装: 44-PLCC(16.59x16.59)
包装: 带卷 (TR)
包括: 警报生成和检测,B7 填充模式,B8ZS 模式,错误检测和计数器,“硬件”模式,透明模式
DS2180A
27 of 35
repeating pattern ...00111000111000...(00111X0 if CCR.3–YELMD–is equal to a 1). In this mode, FT
and FS patterns must be correctly identified by the synchronizer before sync is declared. Clearing RCR.3
causes the synchronizer to search for FT patterns (101010...) without cross-coupling the FS pattern. Frame
sync will be established using the FT information, while multiframe sync will be established only if valid
FS information is present. If no valid FS pattern is identified, the synchronizer will move to the FT
alignment, RLOS will go low, and a false multiframe position may be indicated by RMSYNC. RFER will
indicate when the received S-bit pattern does not match the assumed internal multiframe alignment. This
mode will be used in applications where non-standard S-bit patterns exist. In such applications,
multiframe alignment information can be decoded externally by using the S-bits present at RLINK.
AVERAGE REFRAME TIME
1 Table 9
RCR.2=0
RCR.2=1
FRAME
MODE
MIN
AVG
MAX
MIN
AVG
MAX
UNITS
193S
3.0
3.75
4.5
6.5
7.25
8.0
193E
6.0
7.5
9.0
13.0
14.5
16.0
ms
NOTE:
1. Average Reframe Time is defined here as the average time it takes from the start of sync (rising edge
of RLOS) to the actual loading of the new alignment (on a multiframe edge) into the output receive
timing.
BACKPLANE INTERFACE USING DS2180A AND DS2176 Figure 22
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