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参数资料
| 型号： | DS2180AQN/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 23/35页 |
| 文件大小： | 0K |
| 描述： | IC TRANSCEIVER T1 IND 44-PLCC |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 500 |
| 功能： | 收发器 |
| 接口： | T1 |
| 电路数： | 1 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 3mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.59x16.59） |
| 包装： | 带卷 (TR) |
| 包括： | 警报生成和检测，B7 填充模式，B8ZS 模式，错误检测和计数器，“硬件”模式，透明模式 |
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DS2180A
3 of 35
TRANSMIT PIN DESCRIPTION (40-PIN DIP ONLY) Table 1
PIN
SYMBOL
TYPE
DESCRIPTION
1
TMSYNC
I
Transmit Multiframe Sync. May be pulsed high at multiframe boundaries to
reinforce multiframe alignment or tied low, which allows internal multiframe
counter to free run.
2
TFSYNC
I
Transmit Frame Sync. Rising edge identifies frame boundary; may be pulsed
every frame to reinforce internal frame counter or tied low (allowing TMSYNC to
establish frame and multiframe alignment).
3TCLK
I
Transmit Clock. 1.544 MHz primary clock.
4
TCHCLK
O
Transmit Channel Clock. 192 kHz clock which identifies time slot (channel)
boundaries. Useful for parallel-to-serial conversion of channel data.
5TSER
I
Transmit Serial Data. NRZ data input, sample on falling edge of TCLK.
6TMO
O
Transmit Multiframe Out. Output of internal multiframe counter indicates
multiframe boundaries. 50% duty cycle.
7TSIGSEL
O
Transmit Signaling Select. .667 kHz clock which identifies signaling frame A and
C in 193E framing. 1.33 kHz clock in 193S.
8TSIGFR
O
Transmit Signaling Frame. High during signaling frames, low otherwise.
9TABCD
I
Transmit ABCD Signaling. When enabled via TCR.4, sampled during channel
LSB time in signaling frames on falling edge of TCLK.
10
TLINK
I
Transmit Link Data. Sampled during the F-bit time (falling edge of TCLK) of odd
frames for insertion into the outgoing data stream (193E-FDL insertion). Sampled
during the F-bit time of even frames for insertion into the outgoing data (193S-
External S-Bit insertion).
11
TLCLK
O
Transmit Link Clock. 4 kHz demand clock for TLINK input.
12
13
TPOS
TNEG
O
Transmit Bipolar Data Outputs. Updated on rising edge of TCLK.
PORT PIN DESCRIPTION (40-PIN DIP ONLY) Table 2
PIN
SYMBOL
TYPE
DESCRIPTION
14
INT
1
O
Receive Alarm Interrupt.
Flags host controller during alarm conditions. Active
low, open drain output.
15
SDI
1
I
Serial Data In.
Data for onboard registers. Sampled on rising edge of SCLK.
16
SDO
1
O
Serial Data Out.
Control and status information from onboard registers. Updated
on falling edge of SCLK, tri-stated during serial port write or when CS is high.
17
CS
1
I
Chip Select.
Must be low to write or read the serial port registers.
18
SCLK
1
I
Serial Data Clock.
Used to write or read the serial port registers.
19
SPS
I
Serial Port Select.
Tie to VDD to select serial port. Tie to VSS to select hardware
mode.
NOTE:
1. Multifunction pins. See “Hardware Mode Description."
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2180IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| DS2180Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:PCM Transceiver |
| DS2180QIND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Telecommunication IC |
| DS2181A | 功能描述:网络控制器与处理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2181A+ | 功能描述:网络控制器与处理器 IC CEPT Primary Rate Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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