参数资料
型号: DS21FT40
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA300
封装: BGA-300
文件页数: 52/87页
文件大小: 386K
代理商: DS21FT40
DS21FT40
56 of 87
HDLC CONTROLLER REGISTER LIST Table 14-1
NAME
FUNCTION
HDLC Control Register (HCR)
general control over the HDLC and BOC
controllers
HDLC Status Register (HSR)
key status information for both transmit and
receive directions
HDLC Interrupt Mask Register (HIMR)
allows/stops status bits to/from causing an
interrupt
Receive HDLC Information Register
(RHIR)
status information on receive HDLC
controller
Receive HDLC FIFO Register (RHFR)
access to 64–byte HDLC FIFO in receive
direction
Receive HDLC DS0 Control Register 1
(RDC1)
Receive HDLC DS0 Control Register 2
(RDC2)
controls the HDLC function when used on
DS0 channels
Transmit HDLC Information Register
(THIR)
status information on transmit HDLC
controller
Transmit BOC Register (TBOC)
enables/disables transmission of BOC codes
Transmit HDLC FIFO Register (THFR)
access to 64–byte HDLC FIFO in transmit
direction
Transmit HDLC DS0 Control Register 1
(TDC1)
Transmit HDLC DS0 Control Register 2
(TDC2)
controls the HDLC function when used on
DS0 channels
14.2 HDLC STATUS REGISTERS
Three of the HDLC controller registers (HSR, RHIR, and THIR) provide status information. When a
particular event has occurred (or is occurring), the appropriate bit in one of these three registers will be set
to a one. Some of the bits in these three status registers are latched and some are real time bits that are not
latched. Section 14.4 contains register descriptions that list which bits are latched and which are not.
With the latched bits, when an event occurs and a bit is set to a one, it will remain set until the user reads
that bit. The bit will be cleared when it is read and it will not be set again until the event has occurred
again. The real time bits report the current instantaneous conditions that are occurring and the history of
these bits is not latched.
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