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参数资料
| 型号： | DS21Q42TN |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 90/119页 |
| 文件大小： | 1309K |
| 代理商： | DS21Q42TN |
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DS21Q42
72 of 119
RMTCH1: RECEIVE FDL MATCH REGISTER 1 (Address = 29 Hex)
RMTCH2: RECEIVE FDL MATCH REGISTER 2 (Address = 2A Hex)
(MSB)
(LSB)
RMFDL7
RMFDL6
RMFDL5
RMFDL4
RMFDL3
RMFDL2
RMFDL1
RMFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
RMFDL7
RMTCH1.7
MSB of the FDL Match Code
RMTCH2.7
RMFDL0
RMTCH1.0
LSB of the FDL Match Code
RMTCH2.0
When the byte in the Receive FDL Register matches either of the two Receive FDL Match Registers
(RMTCH1/RMTCH2), SR2.2 will be set to a one and the INT* will go active if enabled via IMR2.2.
15.2.3 Transmit Section
The transmit section will shift out into the T1 data stream, either the FDL (in the ESF framing mode) or
the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (TFDL). When a new value
is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full eight bits has been shifted out, the framer will signal the host
microcontroller that the buffer is empty and that more data is needed by setting the SR2.3 bit to a one.
The INT* will also toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new
value. If the TFDL is not updated, the old value in the TFDL will be transmitted once again. The framer
also contains a zero stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016,
communications on the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no
more than 5 ones should be transmitted in a row so that the data does not resemble an opening or closing
flag (01111110) or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look
for 5 ones in a row. If it finds such a pattern, it will automatically insert a zero after the five ones. The
CCR2.0 bit should always be set to a one when the framer is inserting the FDL. More on how to use the
DS21Q42 in FDL applications is covered in a separate Application Note.
TFDL: TRANSMIT FDL REGISTER (Address = 7E Hex)
[Also used to insert Fs framing pattern in D4 framing mode; see Section 15.3]
(MSB)
(LSB)
TFDL7
TFDL6
TFDL5
TFDL4
TFDL3
TFDL2
TFDL1
TFDL0
SYMBOL
POSITION
NAME AND DESCRIPTION
TFDL7
TFDL.7
MSB of the FDL code to be transmitted
TFDL0
TFDL.0
LSB of the FDL code to be transmitted
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
相关PDF资料 |
PDF描述 |
|---|---|
| DS21Q42T | DATACOM, FRAMER, PQFP128 |
| DS21Q43AT | DATACOM, FRAMER, PQFP128 |
| DS21Q44T | DATACOM, FRAMER, PQFP128 |
| DS21Q44TN | DATACOM, FRAMER, PQFP128 |
| DS21Q48N | DATACOM, PCM TRANSCEIVER, PBGA144 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q43A | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Quad E1 Framer |
| DS21Q43AT | 功能描述:网络控制器与处理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q43AT+ | 功能描述:网络控制器与处理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q43ATN | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:Quad E1 Framer |
| DS21Q43-ATN | 功能描述:网络控制器与处理器 IC Quad E1 Framer RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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