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参数资料
| 型号： | DS2282 |
| 英文描述： | T1 FDL Controller/Monitor Stik |
| 中文描述： | T1 FDL控制器/监视器条 |
| 文件页数： | 12/22页 |
| 文件大小： | 192K |
| 代理商： | DS2282 |
* Service mark of AT&T Communications
DS2282
022798 12/22
T1.403 OPERATION
In order to properly operate on T1 lines running the FDL
under the definition spelled out in the ANSI document
T1.403, the DS2282 must have the 54016 bit in the UBR
set to zero (see “User Register”). The DS2282 will de-
code both the incoming Performance Report Messages
(PRM) and unscheduled messages and provide them
for the user. The DS2282 also collects data on bipolar
violations (BPV), frame errors, CRC–6 errors, and Out–
of–Frame errors (OOF). The DS2282 combines the in-
formation in these registers along with the indication of
local slips via the SLIP signal to create PRMs that are
transmitted once a second via the TLINK signal. Also,
the user can instruct the DS2282 to transmit unsched-
uled messages. For more information on the T1.403
definition, refer to the application note “T1.403 FDL
Message Overview.”
Monitor Registers
There are two sets of monitor registers. The first set
helps support some of the monitoring requirements on
T1 lines as spelled out in documents such as TA–
TSY–000147 (DS1 Rate Digital Service Monitoring Unit
Functional Specifications – October 1987), TR 62411
(Accunet* T1.5 Service Description and Interface Spec-
ifications – December 1988), and the CCITT recom-
mendation G.821. This set consists of three registers,
the Errored Seconds Register (ESR), the Severely Er-
rored Seconds Register (SESR), and the Unavailable
Seconds Register (UASR). Unlike the first set of moni-
tor registers which provides a count of conditioned data,
the second set of monitor registers just provides raw
data counts of events such as CRC–6 errors, bipolar
violations, frame errors, and out of frame errors. The se-
cond set of monitor registers consists of four registers:
the CRC Count Register (CRCCR), the Bipolar Violation
Count Register (BPVCR), the Frame Error Count Reg-
ister (FECR), and the Out Of Frame Count Register
(OOFCR). All of the monitor registers are described be-
low.
ESR: Errored Seconds Register (0C)
.
A 16–bit
register that counts Errored Seconds (ES). An ES is any
one–second time interval with either a frame bit error,
CRC–6 error, OOF event, or controlled slip event.
SESR: Severely Errored Seconds Register
(0D)
.
A 16–bit register that counts Severely Errored
Seconds (SES). A SES is any one–second time interval
with an OOF error event and/or more than 320 CRC–6
errors in it.
UASR: Unavailable Seconds Register (OE)
.
A
16–bit register that counts Unavailable Seconds (UAS).
A UAS is the number of seconds between 10 consecu-
tive SES events (inclusive) and 10 consecutive non–
SES events (exclusive). The DS2282 starts counting
SES events when it receives the first one. If it counts ten
SESs in a row, then it increments the UASR by ten and
decrements the ES and SES by ten. Counts in the ESR
and SESR are inhibited during unavailable seconds.
Once the DS2282 has begun counting unavailable se-
conds, it begins counting non–SES events. At the first
non–SES event, it begins counting Errored Seconds in
a separate register that is not available to the user. If the
DS2282 fails to count ten non–SES events in a row, it
clears both the non–SES count and the register count-
ing Errored Seconds during unavailable seconds. If it
counts ten non–SES events in a row, it will decrement
the UASR by ten and will increment the ESR by the
count in the register counting Errored Seconds during
unavailable seconds. Also, when the DS2282 detects
either an incoming Alarm Indication Signal (AIS) or Re-
ceive Carrier Loss (RCL), it will increment the UASR for
each second either of these conditions exists.
CRCCR: CRC–6 Error Count Register (80)
.
A
16–bit register that records CRC–6 error events. The
DS2282 calculates CRC–6 on the incoming data. Each
time the calculation does not match the CRC–6 code
word in the incoming ESF data stream, then the CRCCR
is incremented by one.
BPVCR: Bipolar Violation Count Register
(81)
.
A 24–bit register that records bipolar violations
(line code violations). Bipolar violations are counted
whether the synchronizer in the DS2282 is in sync (the
RLOS signal is low) or not. If the DS2282 is set up to
receive B8ZS code words, then B8ZS code words are
not counted as bipolar violations.
FECR: Frame Error Count Register (83)
.
A
16–bit register that records errors in the Framing Pat-
tern Sequence (FPS). All individual bit errors in the FPS
pattern (001011) are recorded in the FECR.
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相关代理商/技术参数 |
参数描述 |
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| DS2282/87-22282-000 | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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| DS2286-8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| DS2287-32 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
| DS2287-8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog IC |
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