- 您现在的位置：买卖IC网 > PDF目录1994 > DS2417X/T&R (Maxim Integrated Products)IC TIMECHIP W/INTRPT 1WIRE CSP PDF资料下载
参数资料
| 型号： | DS2417X/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 2/15页 |
| 文件大小： | 0K |
| 描述： | IC TIMECHIP W/INTRPT 1WIRE CSP |
| 标准包装： | 10,000 |
| 类型： | 二进制计数器 |
| 特点： | 唯一 ID |
| 时间格式： | 二进制 |
| 数据格式： | 二进制 |
| 接口： | 1 线 串行 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 6-XBGA，FCBGA |
| 供应商设备封装： | 6-覆晶（2.82x2.54） |
| 包装： | 带卷 (TR) |
DS2417
1–WIRE SIGNALING
The DS2417 requires strict protocols to ensure data integrity. The protocol consists of four types of sig-
naling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write 0, Write 1, and Read
Data. Except for the presence pulse the bus master initiates all these signals.
The initialization sequence required to begin any communication with the DS2417 is shown in Figure 8.
A reset pulse followed by a presence pulse indicates the DS2417 is ready to send or receive data. The bus
master transmits (TX) a reset pulse (tRSTL, minimum 480s). The bus master then releases the line and
goes into receive mode (RX). The 1-Wire bus is pulled to a high state via the pullup resistor. After
detecting the rising edge on the data line, the DS2417 waits (tPDH, 15μs to 60μs) and then transmits the
presence pulse (tPDL, 60μs to 240μs).
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 8
RESISTOR
MASTER
DS2417
MASTER RX "PRESENCE PULSE"
480 s tRSTL < *
480 s tRSTH < **
15 s tPDH < 60 s
60 tPDL < 240 s
MASTER TX
"RESET PULSE"
VPULLUP
PULLUP MIN
VIH MIN
VIL MAX
0V
tRSTH
tRSTL
tPDH
tPDL
tR
V
*
In order not to mask interrupt signaling by other devices on the 1-Wire bus tRSTL + tR should al-
ways be less than 960s.
**
Includes recovery time
READ/WRITE TIME SLOTS
The definitions of write and read time slots are illustrated in Figure 9. The master initiates all time slots
by driving the data line low. The falling edge of the data line synchronizes the DS2417 to the master by
triggering an internal delay circuit. During write time slots, the delay circuit determines when the
DS2417 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit
determines how long the DS2417 will hold the data line low. If the data bit is a “1”, the DS2417 will not
hold the data line low at all.
10 of 15
相关PDF资料 |
PDF描述 |
|---|---|
| DS26502LN+ | IC T1/E1/J1 64KCC ELEMENT 64LQFP |
| DS26503LN+ | IC T1/E1/J1 BITS ELEMENT 64-LQFP |
| DS3105LN+ | IC TIMING LINE CARD 64-LQFP |
| DS3106LN+ | IC TIMING LINE CARD 64-LQFP |
| DS3231MZ+ | IC RTC I2C 8SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2421FP000 | 制造商:Thomas & Betts 功能描述:200A,CON,3P4W,MG,421,3P440V |
| DS2421FR000 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,3P440V |
| DS2421FRA00 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,AGL,3P440V |
| DS2421FRAB0 | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,AB0,3P440V |
| DS2421FRABK | 制造商:Thomas & Betts 功能描述:200A,REC,3P4W,MG,421,ABK,3P440V |
发布紧急采购，3分钟左右您将得到回复。