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参数资料
| 型号： | DS2450S+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 23/25页 |
| 文件大小： | 0K |
| 描述： | IC CONVERTER A/D QUAD 1-W 8-SOIC |
| 产品培训模块： | 1-Wire Communications Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 产品变化通告： | Product Discontinuation 27/Jul/12 |
| 标准包装： | 88 |
| 位数： | 16 |
| 采样率（每秒）： | 1k |
| 数据接口： | 串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 2.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.209"，5.30mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
| 输入数目和类型： | 4 个单端，单极 |
| 产品目录页面： | 1429 (CN2011-ZH PDF) |
DS2450
7 of 24
READ MEMORY [AAH]
The Read Memory command is used to read conversion results, control/status data and alarm settings.
The bus master follows the command byte with a two byte address (TA1=(T7:T0), TA2=(T15:T8)) that
indicates a starting byte location within the memory map. With every subsequent read data time slot the
bus master receives data from the DS2450 starting at the supplied address and continuing until the end of
an eight-byte page is reached. At that point the bus master will receive a 16-bit CRC of the command
byte, address bytes and data bytes. This CRC is computed by the DS2450 and read back by the bus
master to check if the command word, starting address and data were received correctly. If the CRC read
by the bus master is incorrect, a Reset Pulse must be issued and the entire sequence must be repeated.
Note that the initial pass through the Read Memory flow chart will generate a 16-bit CRC value that is the
result of clearing the CRC-generator and then shifting in the command byte followed by the two address
bytes, and finally the data bytes beginning at the first addressed memory location and continuing through
to the last byte of the addressed page. Subsequent passes through the Read Memory flow chart will
generate a 16-bit CRC that is the result of clearing the CRC-generator and then shifting in the new data
bytes starting at the first byte of the next page.
WRITE MEMORY [55H]
The Write Memory command is used to write to memory pages 1 and 2 in order to set the channel-
specific control data and alarm thresholds. The command can also be used to write the single control byte
on page 3 at address 1Ch. The bus master will follow the command byte with a two byte starting address
(TA1=(T7:T0), TA2=(T15:T8)) and a data byte of (D7:D0). A 16-bit CRC of the command byte, address
bytes, and data byte is computed by the DS2450 and read back by the bus master to confirm that the
correct command word, starting address, and data byte were received. Now the DS2450 copies the data
byte to the specified memory location. With the next eight time slots the bus master receives a copy of
the same byte but read from memory for verification. If the verification fails, a Reset Pulse should be
issued and the current byte address should be written again.
If the bus master does not issue a Reset Pulse and the end of memory was not yet reached, the DS2450
will automatically increment its address counter to address the next memory location. The new two-byte
address will also be loaded into the 16-bit CRC-generator as a starting value. The bus master will send
the next byte using eight write time slots. As the DS2450 receives this byte it also shifts it into the CRC-
generator and the result is a 16-bit CRC of the new data byte and the new address. With the next sixteen
read time slots the bus master will read this 16-bit CRC from the DS2450 to verify that the address
incremented properly and the data byte was received correctly. Following the CRC the master receives
the byte just written as read from the memory. If the CRC or read-back byte is incorrect, a Reset Pulse
should be issued in order to repeat the Write Memory command sequence.
Note that the initial pass through the Write Memory flow chart will generate a 16-bit CRC value that is
the result of shifting the command byte into the CRC-generator, followed by the two address bytes, and
finally the data byte. Subsequent passes through the Write Memory flow chart due to the DS2450
automatically incrementing its address counter will generate a 16-bit CRC that is the result of loading (not
shifting) the new (incremented) address into the CRC-generator and then shifting in the new data byte.
The decision to continue after having received a bad CRC or if the verification fails is made entirely by
the bus master. Write access to the conversion read-out registers is not possible. If a write attempt is
made to a page 0 address the device will follow the Write Memory flow chart correctly but the
verification of the data byte read back from memory will usually fail. The Write Memory command
sequence can be ended at any point by issuing a Reset Pulse.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2450S/T&R | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DS2450S+ | 功能描述:模数转换器 - ADC Quad 1-Wire RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| DS2450S+ | 制造商:Maxim Integrated Products 功能描述:SEMICONDUCTOR ((NW)) |
| DS2450S+T&R | 制造商:Maxim Integrated Products 功能描述:IC CONVERTER A/D QUAD 1-W 8-SOIC |
| DS2450S+T&R | 功能描述:模数转换器 - ADC Quad 1-Wire RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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