参数资料
型号: DS26502LN+
厂商: Maxim Integrated Products
文件页数: 34/125页
文件大小: 0K
描述: IC T1/E1/J1 64KCC ELEMENT 64LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: BITS 元件,多路复用器
PLL:
主要目的: T1/E1
输入: 时钟
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:3
差分 - 输入:输出: 无/无
频率 - 最大: 6.312MHz
电源电压: 3.135 V ~ 3.465 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 托盘
产品目录页面: 1430 (CN2011-ZH PDF)
DS26502
16 of 125
4.4 Controller Interface
NAME
TYPE
FUNCTION
INT/
JACKS0
I/O
Active-Low Interrupt/Jitter Attenuator Clock Select 0
INT: Flags host controller during events, alarms, and conditions defined in
the status registers. Active-low open-drain output.
JACKS0: Hardware Mode: Jitter Attenuator Clock Select 0. Set this pin high
for T1 mode operation when either a 2.048MHz, 4.096MHz, 8.192MHz or
16.382MHz signal is applied at MCLK.
TMODE1
I
Transmit Mode Select 1. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
TMODE2
I
Transmit Mode Select 2. In Hardware Mode (BIS[1:0] = 11), this bit is used
to configure the transmit operating mode.
TSTRST
I
Three-State Control and Device Reset. A dual-function pin. A zero-to-one
transition issues a hardware reset to the DS26502 register set. Configuration
register contents are set to the default state. Leaving TSTRST high three-
states all output and I/O pins (including the parallel control port). Set low for
normal operation. Useful for in-board level testing.
BIS[1:0]
I
Bus Interface Mode Select 1, 0. These bits select the controller interface
mode of operation.
BIS[1:0] : 00 = Parallel Port Mode (Multiplexed)
01 = Parallel Port Mode (Nonmultiplexed)
10 = Serial Port Mode
11 = Hardware Mode
AD[7]/
RITD
I/O
Data Bus D[7] or Address/Data Bus AD[7]/Receive Internal Termination
Disable
A[7]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[7].
AD[7]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[7].
RITD: In Hardware Mode (BIS[1:0] = 11), internal receive termination is
disabled when RITD = 1.
AD[6]/
TITD
I/O
Data Bus D[6] or Address/Data Bus AD[6]/Transmit Internal
Termination Disable
A[6]: In nonmultiplexed bus operation (BIS[1:0] = 01), it serves as the data
bus D[6].
AD[6]: In multiplexed bus operation (BIS[1:0] = 00), it serves as the
multiplexed address/data bus AD[6].
TITD: In Hardware Mode (BIS[1:0] = 11), internal transmit termination is
disabled when TITD = 1.
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