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参数资料
| 型号： | DS2740BU+T&R |
| 厂商： | Maxim Integrated |
| 文件页数： | 13/16页 |
| 文件大小： | 304K |
| 描述： | IC CURRENT GAUGE(15BIT) 8UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 功能： | 电流计（13 位） |
| 输入电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-uMAX |
| 包装： | 带卷 (TR) |
DS2740
Table 4. FUNCTION COMMANDS
COMMAND
DESCRIPTION
COMMAND
PROTOCOL
BUS STATE
AFTER COMMAND
PROTOCOL
BUS DATA
Read Data
Reads data from
memory starting at
address XX
69h, XX
Master Rx
Up to 256 bytes
of data
Write Data
Writes data to memory
starting at address XX
6Ch, XX
Master Tx
Up to 256 bytes
of data
1-Wire SIGNALING
The 1-Wire bus requires strict signaling protocols to ensure data integrity. The four protocols used by the
DS2740 are as follows: the initialization sequence (reset pulse followed by presence pulse), write 0, write
1, and read data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2740 is shown in Figure 11.
A presence pulse following a reset pulse indicates that the DS2740 is ready to accept a net address
command. The bus master transmits (Tx) a reset pulse for t
RSTL
. The bus master then releases the line and
goes into Receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After
detecting the rising edge on the DQ pin, the DS2740 waits for t
PDH
and then transmits the presence pulse
for t
PDL
.
Figure 11. 1-Wire INITIALIZATION SEQUENCE
t
R TL
t
PDL
t
R TH
t
PDH
PACK+
PACK-
LINE TYPE LEGEND:
BOTH BUS MASTER AND
DS2740 ACTIVE LOW
DQ
WRITE-TIME SLOTS
A write-time slot is initiated when the bus master pulls the 1-Wire bus from a logic-high (inactive) level
to a logic-low level. There are two types of write-time slots: write 1 and write 0. All write-time slots must
be t
SLOT
in duration with a 1?/SPAN>s minimum recovery time, t
REC
, between cycles. The DS2740 samples the
1-Wire bus line between 15?/SPAN>s and 60?/SPAN>s (between 2?/SPAN>s and 6?/SPAN>s for overdrive speed) after the line falls. If
the line is high when sampled, a write 1 occurs. If the line is low when sampled, a write 0 occurs (see
Figure 12). For the bus master to generate a write 1 time slot, the bus line must be pulled low and then
released, allowing the line to be pulled high within 15?/SPAN>s (2?/SPAN>s for overdrive speed) after the start of the
write-time slot. For the host to generate a write 0 time slot, the bus line must be pulled low and held low
for the duration of the write-time slot.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2740EVKIT+ | 制造商:Maxim Integrated Products 功能描述:HIGH-PRECISION COULOMB COUNTER - Boxed Product (Development Kits) |
| DS2740K | 功能描述:电源管理IC开发工具 RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| DS2740U | 制造商:Maxim Integrated Products 功能描述:HI PRECISION COUL CNTR UMAX(USOP)-8 - Rail/Tube |
| DS2740U/R | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:High-Precision Coulomb Counter |
| DS2740U/T | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:High-Precision Coulomb Counter |
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