参数资料
型号: DS28DG02E-3C+T
厂商: Maxim Integrated
文件页数: 20/34页
文件大小: 0K
描述: IC EEPROM 2KBIT 2MHZ 28TSSOP
标准包装: 2,500
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 2MHz
接口: SPI 3 线串行
电源电压: 2.2 V ~ 5.25 V
工作温度: -40°C ~ 85°C
封装/外壳: 28-SOIC(0.173",4.40mm 宽)裸露焊盘
供应商设备封装: 28-TSSOP 裸露焊盘
包装: 带卷 (TR)
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Figure 12. SPI Status Register
ADDR
N/A
b7
WPEN
b6
RPROT
b5
WD1
b4
WD0
b3
BP1
b2
BP0
b1
WEN
b0
RDYZ
BIT DESCRIPTION
RDYZ: Ready (Read-
Only Bit)
WEN: Write Enabled
(Read-Only Bit)
BP1:BP0: Block Write
Protect
WD1:WD0: Watchdog
Timeout
RPROT: Register
Protection
WPEN: Hardware Write
Protect Enable
BIT(S)
b0
b1
b3:b2
b5:b4
B6
b7
DEFINITION
Indicates whether an EEPROM write cycle is in progress.
Legend : 0 ? ready (normal state); 1 ? write cycle in progress
Indicates whether the device will accept a WRITE instruction; set
through the WREN instruction; cleared through the WRDI instruction or
completion of a valid WRITE or a valid WRSR instruction.
Legend : 0 ? write disabled (power-on default); 1 ? write enabled
These bits specify which of the four user memory blocks are write-
protected (independent of WPEN and WPZ).
Legend : 00b ? not protected (factory default)
01b ? block 3 (0C0h to 0FFh) protected
10b ? blocks 2 and 3 (080h to 0FFh) protected
11b ? blocks 0 to 3 (000h to 0FFh) protected
These bits specify the duration of the watchdog timeout if the watchdog
is enabled (WDE at address 134h = 1).
Legend : 00b ? 1.64s (factory default); 01b ? 820ms
10b ? 410ms; 11b ? 200ms
These are nominal values; for tolerances see Electrical Characteristics.
Specifies whether the writeable addresses in the range of 120h and
higher are write-protected (independent of WPEN and WPZ).
Legend : 0 ? not protected (factory default); 1 ? protected
Specifies whether b7:b2 of the SPI Status register (nonvolatile bits) are
writeable or whether the WPZ pin state controls the write-protection.
Legend: 0 ? writeable (factory default)
1 ? protection controlled by WPZ pin state
If WPEN = 1 and WPZ pin state is 0 the SPI Status register is write-
protected and a WRSR instruction is not valid.
DETAILED DESCRIPTION—SPI INSTRUCTION SET
WREN Write Enable
Before any write access to the device, the WEN bit in the SPI Status register must be set. The only way to set this
bit is through the write-enable instruction. The WEN bit is cleared when the device powers up, after the successful
execution of a write access instruction (WRSR or WRITE) and through WRDI. Figure 13 shows the instruction’s
timing diagram for both SPI communication modes.
WRDI Write Disable
The WRDI instruction can be used to clear the WEN bit of the SPI Status register, e.g., after an unsuccessful write
access instruction. Figure 14 shows the instruction’s timing diagram for both SPI communication modes.
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