参数资料
型号: DS3065WP-100IND+
厂商: Maxim Integrated Products
文件页数: 12/15页
文件大小: 0K
描述: IC SRAM 3.3V 8MB 34POWERCAP MOD
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
格式 - 存储器: RAM
存储器类型: NVSRAM(非易失 SRAM)
存储容量: 8M(1M x 8)
速度: 100ns
接口: 并联
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 34-PowerCap? 模块
供应商设备封装: 34-PowerCap 模块
包装: 托盘
其它名称: 90-3065W+P1I
DS3065WP
3.3V, 8Mb, Nonvolatile SRAM with Clock
V TP
V CC
ABE, AE
AF
Figure 1. Battery-Backup Mode Alarm Waveforms
When the RTC register values match alarm register set-
tings, the alarm flag (AF) is set to 1.
The AE and ABE bits are reset to 0 during the power-up
transition, but an alarm generated during power-up sets
AF to 1. Therefore, the AF bit can be read after system
power-up to determine if an alarm was generated during
the power-up sequence. Figure 1 illustrates alarm timing
during battery-backup mode and power-up states.
Clock Accuracy
The DS3065WP and DS9034I-PCX+ are each individually
tested for accuracy. Once mounted together, the module
typically keeps time accuracy to within Q 1.53 minutes
per month (35ppm) at +25 N C and does not require
additional calibration. For this reason, methods of field
clock calibration are not available and not necessary.
The electrical environment also affects clock accuracy,
and caution should be taken to place the component in
the lowest level EMI section of the PCB layout. For addi-
tional information, refer to Application Note 58: Crystal
Considerations with Dallas Real-Time Clocks (RTCs) .
Power-On Default States
Upon each application of power to the device, the fol-
lowing register bits are automatically set to 0: WDS = 0,
BMB[4:0] = 0, RB0 = 0, RB1 = 0, AE = 0, ABE = 0. All
other RTC bits are undefined.
12
Data-Retention Mode
The device provides full functional capability for V CC
greater than 3.0V and write protects by 2.8V. Data is
maintained in the absence of V CC without additional sup-
port circuitry. The NV SRAM constantly monitors V CC .
Should the supply voltage decay, the NV SRAM auto-
matically write protects itself. All inputs become don’t
care, and all data outputs become high impedance. As
V CC falls below approximately 2.5V (V SW ), the power-
switching circuit connects the lithium energy source to
the clock and SRAM to maintain time and retain data.
During power-up, when V CC rises above V SW , the pow-
er-switching circuit connects external V CC to the clock
and SRAM and disconnects the lithium energy source.
Normal clock or SRAM operation can resume after V CC
exceeds V TP for a minimum duration of t REC .
Freshness Seal
When the DS9034I-PCX+ battery cap is first attached to
a DS3065WP base, the RTC oscillator is disabled and
the lithium battery is electrically disconnected, guaran-
teeing that no battery capacity has been consumed dur-
ing transit or storage.
When V CC is first applied at a level greater than V TP ,
the lithium battery is enabled for backup operation. The
user is required to enable the oscillator (MSB of the
SECONDS register) and initialize the required RTC reg-
isters for proper timekeeping operation.
Maxim Integrated
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