DS3065WP-100IND+ (Maxim Integrated Products) Datasheet资料下载 PDF(6/15 页)

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参数资料

型号：	DS3065WP-100IND+
厂商：	Maxim Integrated Products
文件页数：	6/15页
文件大小：	0K
描述：	IC SRAM 3.3V 8MB 34POWERCAP MOD
产品培训模块：	Lead (SnPb) Finish for COTS Obsolescence Mitigation Program
标准包装：	40
格式 - 存储器：	RAM
存储器类型：	NVSRAM（非易失 SRAM）
存储容量：	8M（1M x 8）
速度：	100ns
接口：	并联
电源电压：	3 V ~ 3.6 V
工作温度：	-40°C ~ 85°C
封装/外壳：	34-PowerCap? 模块
供应商设备封装：	34-PowerCap 模块
包装：	托盘
其它名称：	90-3065W+P1I

DS3065WP

3.3V, 8Mb, Nonvolatile SRAM with Clock

Note 1: All voltages are referenced to ground.

Note 2: These parameters are sampled with a 5pF load and are not 100% tested.

Note 3: t WP is specified as the logical AND of CE with WE for SRAM writes, or CS with WE for RTC writes. t WP is measured from

the later of the two related edges going low to the earlier of the two related edges going high.

Note 4: t WR1 and t DH1 are measured from WE going high.

Note 5: t WR2 and t DH2 are measured from CE going high for SRAM writes or CS going high for RTC writes.

Note 6: t DS is measured from the earlier of CE or WE going high for SRAM writes, or from the earlier of CS or WE going high for

RTC writes.

Note 7: In a power-down condition, the voltage on any pin cannot exceed the voltage on V CC .

Note 8: The expected t DR is defined as accumulative time in the absence of V CC starting from the time power is first applied

by the user. Minimum expected data-retention time is based upon a single convection reflow exposure, followed by an

attachment of a new DS9034I-PCX+. This parameter is assured by component selection, process control, and design. It

is not measured directly during production testing.

Note 9: WE is high for any read cycle.

Note 10: V OE = V IH or V IL . If V OE = V IH during write cycle, the output buffers remain in a high-impedance state.

Note 11: If the CE or CS low transition occurs simultaneously with or later than the WE low transition, the output buffers remain in a

high-impedance state during this period.

Note 12: If the CE or CS high transition occurs prior to or simultaneously with the WE high transition, the output buffers remain in a

high-impedance state during this period.

Note 13: If WE is low or the WE low transition occurs prior to or simultaneously with the related CE or CS low transition, the output

buffers remain in a high-impedance state during this period.

Maxim Integrated

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