参数资料
型号: DS3112N+
厂商: Maxim Integrated Products
文件页数: 17/133页
文件大小: 0K
描述: IC MUX TEMPE T3/E3 256-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: 调帧器,多路复用器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 150mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-PBGA(27x27)
包装: 管件
DS3112
113 of 133
Table 13-3. AC Characteristics–Framer (T3 and E3) Ports
(VDD = 3.3V ±5%, TA = 0°C to +70°C for DS3112; TA = -40°C to +85°C for DS3112N.)
(See
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
22.4
ns
1, 3
FRCLK/FTCLK Clock Period
t1
29.1
ns
2, 3
FTCLK Clock Low Time
t2
9
ns
FTCLK Clock High Time
t3
9
ns
FTD/FTSOF Setup Time to the
Rising Edge or Falling Edge of
FTCLK
t4
3
ns
4
FTD/FTSOF Hold Time from the
Rising Edge or Falling Edge of
FTCLK
t5
3
ns
4
Delay from the Rising Edge or
Falling Edge of FRCLK/FTCLK to
Data Valid on FRDEN/FRD/
FRSOF/FTDEN/FTSOF
t6
3
10
ns
5
NOTES:
1) T3 mode.
2) E3 mode.
3) FRCLK is a buffered version of either FTCLK or HRCLK and, as such, the duty cycle of FRCLK is
determined by the source clock.
4) FTSOF is configured to be an input.
5) FTSOF is configured to be an output.
6) In normal mode, FTD (and FTSOF if it is configured as an input) is sampled on the rising edge of FTCLK and
FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the rising
edge of FRCLK or FTCLK.
7) In inverted mode, FTD (and FTSOF if it is configured as an input) is sampled on the falling edge of FTCLK
and FRDEN, FRD, FRSOF, and FTDEN (and FTSOF if it is configured as an output) are updated on the
falling edge of FRCLK or FTCLK.
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram
FRCLK / FTCLK
Normal Mode
FTD / FTSOF
FRD / FRDEN /
FRSOF / FTSOF /
FTDEN
t4
t5
t6
t1
t2
t3
FRCLK / FTCLK
Inverted Mode
ls_ac
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