- 您现在的位置：买卖IC网 > PDF目录11562 > DS31256 (Maxim Integrated Products)IC CTRLR HDLC 256-CHANNEL 256BGA PDF资料下载
参数资料
| 型号： | DS31256 |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 100/183页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HDLC 256-CHANNEL 256BGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 控制器类型： | HDLC 控制器 |
| 接口： | 串行 |
| 电源电压： | 3 V ~ 3.6 V |
| 电流 - 电源： | 500mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 256-BBGA |
| 供应商设备封装： | 256-BGA（27x27） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页当前第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页
DS31256 256-Channel, High-Throughput HDLC Controller
23 of 183
these signals are always outputs during the address phase. They remain outputs for the data phase(s) in a write
transaction and become inputs for a read transaction. When the device is a target, these signals are always inputs
during the address phase. They remain inputs for the data phase(s) in a read transaction and become outputs for a
write transaction. When the device is not involved in a bus transaction, these signals remain tri-stated. These
signals are always updated and sampled on the rising edge of PCLK.
Signal Name:
PCBE0/PCBE1/PCBE2/PCBE3
Signal Description:
PCI Bus Command and Byte Enable
Signal Type:
Input/Output (tri-state capable)
Bus command and byte enables are multiplexed onto the same PCI signals. During an address phase, these signals
define the bus command. During the data phase, these signals are used as byte enables. During data phases,
PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is high, the associated byte is
invalid; when low, the associated byte is valid. When the device is an initiator, this signal is an output and is
updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction, these signals are tri-stated.
Signal Name:
PPAR
Signal Description:
PCI Bus Parity
Signal Type:
Input/Output (tri-state capable)
This signal provides information on even parity across both the PAD address/data bus and the PCBE bus
command/byte enable bus. When the device is an initiator, this signal is an output for writes and an input for reads.
It is updated on the rising edge of PCLK. When the device is a target, this signal is an input for writes and an
output for reads. It is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PPAR is tri-stated.
Signal Name:
PFRAME
Signal Description:
PCI Cycle Frame
Signal Type:
Input/Output (tri-state capable)
This active-low signal is created by the bus initiator and is used to indicate the beginning and duration of a bus
transaction.
PFRAME is asserted by the initiator during the first clock cycle of a bus transaction and remains
asserted until the last data phase of a bus transaction. When the device is an initiator, this signal is an output and is
updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on the
rising edge of PCLK. When the device is not involved in a bus transaction,
PFRAME is tri-stated.
Signal Name:
PIRDY
Signal Description:
PCI Initiator Ready
Signal Type:
Input/Output (tri-state capable)
The initiator creates this active-low signal to signal the target that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the
PTRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction,
PIRDY is deasserted when the initiator cannot
temporarily accept or send data, and a wait state is invoked. When the device is an initiator, this signal is an output
and is updated on the rising edge of PCLK. When the device is a target, this signal is an input and is sampled on
the rising edge of PCLK. When the device is not involved in a bus transaction,
PIRDY is tri-stated.
Signal Name:
PTRDY
Signal Description:
PCI Target Ready
Signal Type:
Input/Output (tri-state capable)
The target creates this active-low signal to signal the initiator that it is ready to send/accept or to continue
sending/accepting data. This signal handshakes with the
PIRDY signal during a bus transaction to control the rate
at which data transfers across the bus. During a bus transaction,
PTRDY is deasserted when the target cannot
temporarily accept or send data, and a wait state is invoked. When the device is a target, this signal is an output
and is updated on the rising edge of PCLK. When the device is an initiator, this signal is an input and is sampled
on the rising edge of PCLK. When the device is not involved in a bus transaction,
PTRDY is tri-stated.
相关PDF资料 |
PDF描述 |
|---|---|
| DS3112N | IC MUX TEMPE T3/E3 IND 256-BGA |
| CONREVSMA002-SMD | CONN RP-SMA FEMALE R-A SMD |
| DS21FT44N | IC FRAMER E1 4X3 12CH IND 300BGA |
| PIC16F1933-E/SP | MCU 8BIT 4K FLASH 28-DIP |
| DS21FF42+ | IC FRAMER T1 4X4 16CH 300-BGA |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS31256+ | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256B | 功能描述:输入/输出控制器接口集成电路 256Ch High Thruput HDLC Cntlr RoHS:否 制造商:Silicon Labs 产品: 输入/输出端数量: 工作电源电压: 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:QFN-64 封装:Tray |
| DS31256DK | 功能描述:网络开发工具 RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS31256-W+ | 制造商:Maxim Integrated Products 功能描述:ENVOY 256 CHANNEL HDLC - WAIVER - Rail/Tube |
| DS312BNC | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Industrial Control IC |
发布紧急采购，3分钟左右您将得到回复。