参数资料
| 型号： | DS3153+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/61页 |
| 文件大小： | 0K |
| 描述： | IC LIU DS3/E3/STS-1 144-CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 160 |
| 类型： | 线路接口装置（LIU） |
| 驱动器/接收器数： | 2/2 |
| 规程： | DS3 |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 144-BGA，CSPBGA |
| 供应商设备封装： | 144-TECSBGA（13x13） |
| 包装： | 托盘 |
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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
22 of 61
6. RECEIVER
Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line. Typically, the
receiver interfaces to the incoming coaxial cable (75
Ω) through a 1:2 step-up transformer. Figure 1-1 shows the
arrangement of the transformer and other recommended interface components. Table 11-A specifies the required
characteristics of the transformer. The receiver expects the incoming signal to be in B3ZS- or HDB3-coded AMI
format.
Optional Preamp. The receiver can be used in monitoring applications, which typically have series resistors with a
resistive loss of approximately 20dB. When the RMON input pin is high, the receiver compensates for this resistive
loss by applying approximately 14dB of flat gain to the incoming signal before sending the signal to the
AGC/equalizer block where additional flat gain is applied as needed.
Automatic Gain Control (AGC) and Adaptive Equalizer. The AGC circuitry applies flat (frequency independent)
gain to the incoming signal to compensate for flat losses in the transmission channel and variations in transmission
power. Since the incoming signal also experiences frequency-dependent losses as it passes through the coaxial
cable, the adaptive equalizer circuitry applies frequency-dependent gain to offset line losses and restore the signal.
The AGC/equalizer circuitry automatically adapts to coaxial cable losses from 0 to 15dB, which translates into 0 to
380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent).
The AGC and the equalizer work simultaneously but independently to supply a signal of nominal amplitude and
pulse shape to the clock and data recovery block. The AGC/equalizer block automatically handles direct (0 meters)
monitoring of the transmitter output signal.
Clock and Data Recovery (CDR). The CDR block takes the amplified, equalized signal from the AGC/equalizer
block and produces separate clock, positive data, and negative data signals. The CDR requires a master clock. If
the signal on the appropriate MCLK pin is toggling, the LIU selects the MCLK signal as its master clock. If the
appropriate MCLK pin is wired high, the LIU uses the signal on the TCLK pin as the master clock. The appropriate
MCLK is selected based on the settings of the E3M and STS mode pins or register bits.
The receiver locks onto the incoming signal using a clock recovery PLL. The status of the PLL lock is indicated in
the RLOL status bit. The RLOL bit is set when the difference between recovered clock frequency and MCLK
frequency is greater than 7900ppm and cleared when the difference is less than 7700ppm. A change of state of the
RLOL status bit can cause an interrupt on the
INT pin if enabled to do so by the RLOLIE interrupt-enable bit. Note
that if MCLK is not present, or MCLK is high and TCLK is not present, RLOL is not set.
Loss-of-Signal (LOS) Detector. The receiver contains analog and digital LOS detectors. The analog LOS detector
resides in the AGC/equalizer block. If the incoming signal level is less than a signal level approximately 24dB below
nominal, analog LOS (ALOS) is declared. The ALOS signal cannot be directly examined, but when ALOS occurs
the AGC/equalizer mutes the recovered data, forcing all zeros out of the data recovery circuitry and causing digital
LOS (DLOS), which is indicated by the
RLOS pin and the RLOS status bit. ALOS clears when the incoming signal
level is greater than or equal to a signal level approximately 18dB below nominal.
The digital LOS detector declares DLOS when it detects 175
±75 consecutive zeros in the recovered data stream.
When DLOS occurs, the receiver asserts the
RLOS pin (hardware mode) or the RLOS status bit (CPU bus mode).
DLOS is cleared when there are no EXZ occurrences over a span of 175
±75 clock periods. An EXZ occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive zeros in
the E3 mode. The
RLOS pin goes inactive (high) when the DLOS condition is cleared. In CPU bus mode, a change
of the RLOS status bit can cause an interrupt on the
INT pin if enabled to do so by the RLOSIE interrupt-enable bit.
The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector, which
asserts RLOS when it counts 175
±75 consecutive zeros coming out of the CDR block and clears RLOS when it
counts 175
±75 consecutive pulse intervals without excessive zero occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector and the
DLOS detector, as follows:
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3153+ | 功能描述:网络控制器与处理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3153DK | 功能描述:网络开发工具 DS3153 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS3153N | 功能描述:网络控制器与处理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3153N# | 功能描述:网络控制器与处理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3153N+ | 功能描述:网络控制器与处理器 IC Triple DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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